The Pci Bus Steven Blaize Advance Computer

Published Date: 02 Nov 2017

Introduction

The PCI (Peripheral Component Interconnect) bus is a processor independent bus which is used to attach additional devices to the central processing unit. The PCI delivers better performance with its popular high bandwidth. The current standard allows up to a 64 bit transfer. This high speed delivers better performance for audio and video devices especially high graphic demanded devices, network interface controllers, disk controllers and other high speed devices. The PCI bus is designed to support both single processors and multiprocessor systems. It provides a general purpose set of functions which makes use of synchronous timing and a centralized arbitration scheme.

History

The PCI bus was first began construction in 1990 then released in 1992 when Intel released their Pentium-based system. The Primary goal of the PCI bus was to advance the interface allowing original equipment manufacturers (OEMs) or users to upgrade the I/O of personal computers. The fact that there is a PCI bus in almost every PC and Server today makes the PCI bus a major turn point in making the personalized computer widely marketable. The first PCI bus had a clock speed of 33MHz. The PCI bus offered many advantages over previous bus implementations. Some of the important advantages were: processor independence, buffered isolation, bus mastering, and true plug-and-play operation. "Buffered isolation essentially isolates, both electrically and by clock domains, the CPU local bus from the PCI bus. This feature adds two main benefits to system performance. The first is the ability to run concurrent cycles on the PCI bus and CPU bus; the second allows an increase in the CPU local bus frequency, independent of the PCI bus speed and loading." Using bus mastering, Instead of waiting on the host CPU to give access and permission, the PCI boards can gain access to the PCI bus through an arbitration process directly. This will result in a reduction of overall latency on servicing I/O transactions. "Plug-and-play operation, which allows devices to be automatically detected and configured, eliminated the manual setting of switches and jumpers for base address and DMA interrupt that frustrated ISA-based board users."

The PCI bus has grown largely since 1990. The main three variations of the bus are the Conventional PCI, the PCI-X and the PCI Express. The evolution of the bus in its early lifetime is given as follows: The PCI v1.0 with full specifications was released in 1992. In 1993 v2.0 was released with the addition on the PCI plug and play Configuration model. In 1994 v2.1 was released with addition feature of PCI power management. The PCI Hot Plug which allows you to remove and replace devices without turning off or restarting the computer was adding in 1998 with the release of PCI v2.2. The Mini PCI otherwise known as the PCI-X version 1.0 was released in 1999. A standard Hot Plug v1.0 was released in 2001. In 2002, the PCI-X v2.0, PC! v2.3 and the new PCI Express v1.0 was released. Faster clock speed, on the PCI-X v2.0 (533 MHz) and the PCI Express (2.5 GHz) made this a great year for the PCI. In 2003 there were new additions to the PCI Express v1.0a. Some of the features were the ExpressCard, PCI Express to PCI/PCI-X Bridge Specification v1.0 and the PCI Express Mini Card v1.0.

PCI SIG

The PCI SIG (Peripheral Component Interconnect Special Interest Group was founded in 1992 by Intel to establish the specifications for the PCI conventional, PCI-X and PCI Express (PCIe) computer buses. It is a nonprofit corporation with a consortium of more than 800 companies. The consortium is governed by a Board of Directors of nine people elected by the whole consortium. They are mostly elected from some of the Major PCI companies. The current members of the Board of Directors are employees of the following companies: Ramin Neshati of Intel, Al Yanes of IBM, Tony Pierce of Dell, Michael Krause of Hewlett-Packard, Michael Diamond of NVIDIA, Rick Wietfeldt of Qualcomm, Reen Presnell of VTM, Inc., Richard Solomon of LSI Corporation, Rick Eads of Agilent Technologies and Betty Luk of Advanced Micro Devices, Inc.

"The PCI SIG is chartered to:

Maintain the forward compatibility of all PCI revisions or addenda

Contribute to both the establishment of PCI as an industry-wide standard and to the technical longevity of the PCI architecture

Maintain the PCI specification as a simple, easy-to-implement, stable technology that supports the spirit of its design

It continues to promote and evolve the PCI standards to meet the industry’s needs."

PCI bus structure

There are two common configuration of the PCI bus which is 32 bit data lines and the 64 bit data line. Calculated with the Bus Clock frequency the bandwidth of the data lines gives you the speed of transfers. For example: a 32 bit data line with a clock speed of 33 MHz would give you 132 MB/s while with 66MHz is 264 MB/s transfer rate. A 64 bit data line with a clock speed of 33 MHz would give you 256 MB/s while with 66MHz is 512 MB/s transfer rate. One of the most current effective ways of increasing the speed of the PCI bus is increasing the clock speed.

The pins on the PCI bus are divided into many different categories. The categories are as follows:

System Pins: 1) The clock pin provides timing for all transactions and is supplied and sampled by the input on the rising edge. Clock rates up to 64MHz are supported. 2) Reset pin- It forces all PCI specific registers, sequencers and signals to an initialized state.

Address and Data Pins: 1) Address/Data 0::31- there are 32 lines that are multiplexed for data and addresses. 2) Bus Command and Byte enable C/BE 0::3- During the data phase, the lines indicate which of the four byte lanes carry meaningful data. 3) PAR- Provides even parity across AD and C/BE lines one clock cycle later. The master drives PAR of address and write data phases.

Interface Control Pins: 1) FRAME- Driven by current master to indicate the start and duration of a transaction. It is asserted at the start and de-asserted when the initiator is ready to begin the final data phase. 2) Initiator ready (IRDY) - Driven by current bus master. During a read, indicates that the master is prepared to accept data; during a write indicates that valid data are present on AD lines. 3) Target ready (TRDY) - Driven by the target. During the read, indicates that valid data is present on AD; during a write indicates the target is ready to accept data. 4) STOP- Indicates that current target wishes to initiator to stop the current transaction. 5) Initialization Device Select (IDSEL) - used as a chip select during configuration read and write transaction. 6) Device Select (DEVSEL) - Asserted by target when it has recognized its address. Indicates to current target whether any device has been selected.

Arbitration Pins: 1) REQ- Indicates to the arbiter that this device requires use of the bus. This is a device-specific point-to-point line. 2) GNT- Indicates to the device that the arbiter has granted bus access. This is a device-specific point-to-point line.

Error Reporting Pins: 1) Parity Error (PERR) - Indicates a data parity error is detected by a target during a write data phase or y an initiator during a read data phase. 2) System Error (SERR)- May be pulsed by any device to report address parity errors and critical errors other than parity.

Interrupt Pins: The INTA, INTB, INTC, and INTD lines are used to request interrupts. They are used to gain request from PCI devices. Each PCI Device has its own interrupt line to an interrupt controller.

Cache Support Pins:1) Snoop Backoff (SBO)- Indicates a hit to a modified line. 2) Snoop Done (SDONE) - Indicates the status of the snoop for the current access. Is asserted when snoop has been completed.

64 Bit Bus Extension Pins: 1) Address data pins 32::63- Used as multiplexed address and data lines used to expand PCI bus from 32 bit to 64 bits 2)Bus Command and Byte enable (C/BE 4::7)- 3)REQ64 – used to request use of 64 bit transfer. 4) ACK64- Indicates target is capable to perform a 64 bit transfer 5) PAR64- Provides even parity across extended AD and C/BE lines one clock cycle later.

JTAG/Boundary Scan Pins: 1) Test Clock- used to clock state information and test data into and out of the device during boundary scan. 2) Test Input- used to serially shift test data and instructions into the device. 3) Test output- used to serially shift test data and instructions out of the device. 4) Test mode select- Used to Control state of test access port controller. 5) Test rest- Used to Initialize test access port controller.

http://cdnsupport.gateway.com/s/motherbd/intel2/2521743/252174303.jpgPCI Bus pin slot for connection to the system bus.

PCI Commands

There are 16 possible command signals with 0100,0101,1000,1001 used as reserved. The 12 mainly used signals are Interrupt Acknowledge, Special Cycle, I/O read, I/O write, Memory read, memory write, Configuration read, Configuration write, Multiple Memory read, Dual Address Cycle, Memory- Read Line and Memory Write and Invalidate.

Interrupt Acknowledge is a read command intended for the device that acts as an interrupt controller on the PCI bus. The AD lines are not being used during the address phrase and the byte enable lines indicate the size of the interrupt identifier to be returned. The Special Cycle is used to broadcast a message to one or more devices attached to the bus. The I/O read and write is used for data transfer between the originator and the I/O controller. Address lines are used here to determine which device is being written to or read from. Memory read and write commands are used to specify the transfer of a burst of data. The interpretation of these commands depends on whether or not the memory controller on the PCI bus supports the PCI protocol for transfer. The different between the three memory reads are: Memory read bursting one-half or less of cache line for cache memory or 2 data transfer cycles or less for non-cacheable memory. Memory read Line bursting one-half to three cache lines for cache memory or 3-12 data transfer cycles for non-cacheable memory. Memory read multiple bursting more than three cache lines for cache memory or more than 12 data transfer cycles for non-cacheable memory. The Memory Write and Invalidate command is used to transfer data in one or more cycle and guarantees that at least one cache line is written. This cache function is writing back a line to memory. The Configuration read and write commands are a used when configuring a device the write command updates a configuration parameters in a device.

PCI Arbitration

The PCI bus uses a central synchronous system when it comes to Arbitration. Each PCI device has its own unique request and grant signal which is attached to the central PCI arbiter. Access to the bus could be given easily by a short request-grant transaction. The priority scheme for the bus is not always based on the PCI specifications. The PCI Arbitration Algorithm may be First come first served, a round robin approach, shortest job first or whichever priority scheme the manufacture sees desirable. For each transfer there is one address cycle followed by one or more data cycles.

PCI-X

The PCI-X is a newer, higher speed version of the conventional PCI standard. PCI-X is built upon the same design, protocols, signals, and connector as traditional PCI. THE PCI-X is backwards compatible so it also works with conventional PCI Devices. The PCI-X 66 and PCI-X 133 devices could transfer data up to 133 MTS, or over 1 GB/s for a 64-bit device. The PCI-X version 2.0 supports signaling speeds up to 533MTS. The PCI-X 266 and PCI-X 533, offers up to 4.3 GB/s of bandwidth, 32 times faster than the first generation of PCI. Another major feature of the PCI-X is it enhances system reliability. "ECC support has been added both for the header and payload, providing automatic single-bit error recovery and double-bit error detection. These new standards keep pace with upcoming advances in high-bandwidth business-critical applications such as Fibre Channel, RAID, networking, InfiniBandâ„¢ Architecture, SCSI, and iSCSI."(PCI SIG)

The recycle of many of the design elements from the conventional PCI and PCI-X1.0b standards eases design and implementation migration. Migration to PCI-X 266 and PCI-X 533 is further simplified by retaining hardware and software compatibility with previous generations of PCI and PCI-X. As a result, new designs can immediately connect with hundreds of PCI and PCI-X products that are currently available. The combination of backwards compatibility and ease of migration provides investment protection for customers, developers, and manufacturers of existing PCI and PCI-X technologies as they migrate to PCI-X 266 and PCI-X 533.

PCI-X 2.0 also includes new features that will enhance applications in the future. It defines a new 16-bit interface width specially designed for those applications that are constrained by space, such as embedded RAID controllers, or portable applications.

Important features of PCI-X

Doubles and Quadruples PCI-X bandwidth.

Full hardware and software backward compatibility to previous generations of PCI.

Builds upon tens of man-centuries of development.

Uses the same form factor, pin-outs, connector, bus widths, and protocols.

Enables 10Gb Ethernet, 10Gb Fibre Channel, InfiniBandâ„¢ Architecture, and other IO technologies.

Full RAS support including ECC.

Performance 32 times higher than the first generation of PCI.

PCI Express

The PCI Express Architecture is specified in layers (Physical, Data Link, Software, and Transaction). Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The basic physical layer consists of a dual-simplex channel that is implemented as a transmit pair and a receive pair. The Data link layer adds sequence numbers and Cyclic Redundancy Code (CRC) to these packets to create a highly reliable data transfer mechanism. The software layers will generate read and write requests that are transported by the transaction layer to the I/O devices using a packet-based, split-transaction protocol.

PHYSICAL LAYER

The fundamental PCI Express link consists of a transmit pair signal and a receive pair of two, low-voltage, differentially driven pairs of signals. The initial frequency is 2.5Gb/s/direction and this is anticipated to increase with silicon technology advances to the 10Gb/s/direction. The physical layer transports packets between the data link layers of two PCI Express devices. The bandwidth of a PCI Express link may be linearly scaled by adding signal pairs to form multiple lanes. The physical layer supports x1, x2, x4, x8, x12, x16 and x32 lane widths (Figure 2). During initialization, each PCI Express link is set up following a negotiation of lane widths and frequency of operation by the two devices at each end of the link. No firmware or operating system software is involved. The PCI Express architecture comprehends future performance enhancements via speed upgrades and advanced encoding techniques. The future speeds, encoding techniques or media would only impact the physical layer.

DATA LINK LAYER

The primary role of a Data link layer is to ensure reliable delivery of the packet across the PCI

Express link. The link layer is responsible for data integrity and adds a sequence number and a CRC to the transaction layer packet. Most packets are initiated at the Transaction Layer. A credit-based, flow control protocol ensures that packets are only transmitted when it is known that a buffer is available to accept this packet at the other end. This eliminates any packet retries, and their associated waste of bus bandwidth due to resource constraints. The Data Link Layer will automatically retry a packet that was signaled as corrupted.

TRANSACTION LAYER

The transaction layer receives read and write requests from the software layer and creates request packets for transmission to the link layer. All requests are implemented as split transactions and some of the request packets will need a response packet. The transaction layer also receives response packets from the link layer and matches these with the original software requests. Each packet has a unique identifier that enables response packets to be directed to the correct originator. The packet format supports 32bit memory addressing and extended 64bit memory addressing. Packets also have attributes such as "no-snoop," "relaxed-ordering" and "priority" which may be used to optimally route these packets through the I/O subsystem. The transaction layer supports four address spaces: it includes the three PCI address spaces (memory, I/O and configuration) and adds a Message Space. PCI 2.2 introduced an alternate method of propagating system interrupts called Message Signaled Interrupt (MSI). Here a special-format memory write transaction was used instead of a hard-wired sideband signal.

The PCI Express specification re-uses the

MSI concepts as a primary method for interrupt processing and use Message Space to support all prior side-band signals, such as interrupts, power-management requests, resets, and so on, as in-band Messages. Other "special cycles" within the PCI 2.2 specification, such as Interrupt acknowledge, are also implemented as in-band Messages. You could think of PCI Express

Messages as "virtual wires" since their effect are to eliminate the wide array of sideband signals currently used in a platform implementation.

SOFTWARE LAYERS

Software compatibility is of paramount importance for a Third Generation general purposes I/O interconnect. There are two facets of software compatibility; initialization, or enumeration, and run time. PCI has a robust initialization model wherein the operating system can discover all of the add-in hardware devices present and then allocate system resources, such as memory, I/O space and interrupts, to create an optimal system environment. The PCI configuration space and the programmability of I/O devices are key concepts that are unchanged within the PCI Express Architecture. The run-time software model supported by PCI is a load-store, shared memory model this is maintained within the PCI Express Architecture which will enable all existing software to execute unchanged. New software may use new capabilities.

MECHANICAL CONCEPTS

The low signal-count of a PCI Express link will enable both an evolutionary approach to I/O subsystem design and a revolutionary approach that will encourage new system partitioning.

Evolutionary Design Initial implementations of PCI Express-based add-in cards will coexist alongside the current PCI-form factor boards. As an example connection; a high-bandwidth link, such as four-lane connection to a graphics card, would use a PCI Express connector that would be placed alongside the existing PCI connector in the area previously occupied by an ISA connector.

http://www.newron-system.com/IMG/jpg/nic709-pci100_perspective.jpgfigure 1 PCI Extension devicehttp://www.idg.no/multimedia/archive/00045/pcie_45221a.jpgFigure 2

http://www.icpamerica.com/images/PCI-8S-Large.jpgFigure 3 PCI Pin Slots extension