The Model Based Paradigm And Uml

Published Date: 02 Nov 2017

1 Introduction

An embedded system is a special-purpose computer system which is generally part of a larger physical system and provides a dedicated, and sometimes programmable, functionality to its ambient environment. Nowadays, such systems are heavily used in airplanes, automobiles, industrial systems, cameras, medical equipments, house-hold appliances and inside so many other application areas.

In recent years, the complexity of the embedded systems have increased tremendously, along with the decreased technological figures. The time-to-market is also shrinking, imposing challenges for the designers to adopt new design methods.

As an answer to the new capabilities and pressures, embedded computing systems hence moved towards on-chip multiprocessing technologies. New architectures are brought into the context of on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Distributed on-chip architectures (DocA) or multiprocessor system-on-chip (MPSoC) paradigm gains increasing support from system designers. MPSoC is seen as one of the foremost means through which performance gains are still to be sustained even after Moore’s law may become decrepit [20]. The most common DocA / MPSoC platforms are network-on-chip (NoC) [1], and segmented bus platforms [12][15].

As the complexity of the application requirements is increasing with time, the designers are facing difficulty while designing applications targeting MPSoC. However, it has also been a challenge to fully benefit from the features of MPSoC platforms. One of the reasons behind the difficulties in MPSoC development is the deficiency of systematic design methodologies [20].

The platform-based design approach [3][26][27] does provide the means to address the challenges. The principle behind the approach is to separate the functionality of an application with the structure and communication features of a hardware platform at several levels of abstraction. This not only eases the design process, but also delivers efficiency to work in specific aspects of the system developed by different members of the design team. The essential step in this approach is the mapping process where functions of the application to be implemented are assigned (mapped) to the components of the hardware platform spread within a single chip or on a number of chips. Targeting initially single chip designs, the approach gains even more importance in the context of DocA / MPSoC.

The existing design methodologies don’t provide full automation in every level of the development process, and sometimes, the communication characteristics of the platforms and the employed devices also do not match. In order to offer an optimum match, platform specific characteristics must be taken into consideration for each application.

Moreover, the design productivity gap with the MPSoC paradigm remains one of a key challenge with the existing design methodologies. This challenge can be addressed by developing new computer-aided design (CAD) tools/frameworks, based on newer design methods together with reusable elements inside. This will not only enable us to take full advantages from MPSoC platforms, but it will further satisfy other important challenges e.g. time-to-market, quality of results, costs, etc.

Design decisions localized at higher system abstraction levels are known to bear the most impact on the quality of the eventual system implementation. Given the complexity of modern on-chip multiprocessor solutions, this seems to gain even more in importance. On the other hand, optimality of design is strictly connected to platform parameters; hence, such platform-level aspects, if taken into account at high abstraction levels will support a solution that maximizes the benefits of the features exposed by the platform. The specific platform we consider in this study is the SegBus platform [15], which is basically an on-chip communication platform to provide communication infrastructure between the connected IP-cores in an MPSoC environment.

The two basic and most commonly used approaches of the design methodologies used for the embedded system design are: top-down and meet-in-the-middle [2]. The top-down methodology begins with a particular model of computation (MOC) which defines initially a system platform or system structure with required components. Next, a high-level system specification is refined iteratively by decomposing components with respect to decreasing level of abstraction until enough details are gathered for each component. The design is then partitioned into hardware and software units, and co-designed. Hence, the approach is also well-known as hw/sw co-design. On the other hand, a bottom-up approach is an inverse approach of the top down flow where, firstly, individual components are built, and integrated afterwards to eventually develop a target system.

In the meet-in-the-middle [2] approaches, the application(s) and the platform are developed independently. The platform is developed by employing a bottom-up design flow where the low-level aspects of the platform are considered, whereas the application is developed by following a top-down flow starting from the high-level aspects of the application. When both specifications are complete, the application is then mapped on to the platform and this is a major and distinguished feature of the meet-in-the-middle approach. This approach is heavily dependent on a comprehensive library of software and hardware elements which in return reduces design time and efforts despite the establishment of such library requires significant efforts beforehand.

In this thesis, our work is highly influenced by the meet-in-the-middle approach because of two important reasons. First, we have a particular platform (the SegBus platform) and it is intended to be used as an implementation platform where a number of applications from the same family can be executed. Second, the platform promotes the reuse of intellectual property (IP) components at different levels of abstraction which enables us to tackle other important complexity challenges e.g. design cost, time-to-market, etc.

Figure 1: The Y-chart approach [23].

1 The Y-chart approach

The Y-chart [22][23] is a generic and iterative design space exploration methodology for designing platform-based systems. The methodology is based on the meet-in-the-middle flow where the application and implementing platform are developed independently but the platform is fine-tuned iteratively to provide performance required by a set of targeted applications at a certain level of abstraction.

In this methodology, an instance of the platform is known as a configuration. In a mapping process, the implementation of the application onto a platform configuration is performed. The general overview of this approach is depicted in Figure 1. The artifacts (application(s), platform/architecture and mapping) are equally important to achieve a best / optimal configuration for targeted performance scores. The performance aspects of the mapped application running on a platform configuration are examined in Performance Analysis step where performance numbers determine the efficiency of chosen configuration. If the configuration is not best / optimal, then we get another chance to further explore the design space to produce a new configuration and the process continues iteratively. This way, we can truly exploit all the essential features of the employed platform in order to acheive target performance goals.

2 The Model-Based Paradigm and UML

Computing systems have been around for quite a few decades and their increasing complexity with the time is a known challenging factor for all those associated with their design in anyway. In the start, it was relatively easy to design and implement such systems with some low-level languages. But as the time went by, system specification became more difficult for newer systems and the designers realized that the abstraction levels have to be raised. Consequently, high-level programming languages like C, Fortran and Pascal were developed and employed in the 1970s. By the time, these high-level programming languages were not competent enough to tackle the increasing complexities of specifications, and as a result, the object-oriented paradigm (OOP) came into existence. The paradigm was based on a simple idea - Everything is an object. Later, the object-oriented paradigm gained popularity among designers and larger systems were developed by employing this paradigm. However, the ever growing complexities of the systems also crossed the limits of object-oriented paradigm and a new paradigm introduced: the model driven paradigm. The paradigm is based on a simple idea: Everything is a model. In fact, the idea is not so new because it has been used previously with database systems.

The software engineering community gradually adopted the model based paradigm, and as a result, the system specification moved from textual description (C, C++, Java) to visual/graphical modeling languages, which provide a higher-level of abstractions in modeling environments for system specification and Unified Modeling Language (UML) [54] is one of them.

A notation is a graphical entity, and basically, it is the syntax of a modeling language. Primarily, UML is general-purpose modeling language which includes a set of graphical notations which are used in a particular diagram (e.g., class diagram, state diagram, ...) for specifying various aspects of a software system in a broader manner. It can be applied to a variety of application domains, most importantly to object-oriented and component-based systems. Furthermore, the UML’s extensibility mechanism (i.e., stereotypes, tagged values and constraints) enables us to introduce new building blocks from the existing ones. This capability opens a door to raise the abstraction level further higher - a modeling area, termed as, domain specific modeling (DSM). For DSM, UML is extensively applied initially to build domain specific language (DSL) based on an associated UML profile targeted for a particular domain (discussed briefly in chapter 4).

The paradigm shift from programming languages to modeling languages, as discussed earlier, for system specification has introduced a new methodology for software engineering known as the Model Driven Architecture (MDA) [50] promoted by the Object Management Group (OMG). The primary focus of MDA is on models, automation (by model transformations) and code generation which in turns, shifts the targeted system’s design concerns from low-level implementation to high-level solution modeling. UML is the key enabling technology for MDA, and thus, it is the default modeling language for MDA. The model transformation is a key feature in MDA approach. It enables us to transform a model from one abstraction level to another, and hence, it is the driving force which shifts models from high-level of abstractions to lower-levels, and finally towards implementation. The important kinds of model transformation are: model-to-model (M2M), model-to-text (M2T), etc.. We employ model-to-text (M2T) transformation in our approach, as we will discuss in Chapter 5.

In a networking session [21] few years ago, on-chip MPSoCs have been realized as the preferred architecture for complex embedded systems in the future. Still, as discussed earlier, a lack of proper tools, design frameworks and methodologies create hesitation in Electronic Design Automation (EDA) community to declare it as the mainstream architecture for embedded systems implementations. In this thesis, we intend to take a small step further by making use of UML and MDA, towards developing a unitary framework for design and verification of applications targeting an MPSoC platform.

3 Design and Verification Challenges

A few of the challenges in designing applications targeting DocA (in general) and SegBus (in particular) that we address here can be stated as follows.

CoD - complexity of design. In the context of hardware/software based systems, the term complexity refers to amount of unsurity in getting confidence of moving from one phase of design process to another. Embedded systems are essentially complex [41]. This is particularly true for modern embedded systems comprising complex application requirements and always demanding new features. The factor of complexity increases due to a number of specific design constraints. Some of these design constraints includes:

real-time constraints related to particular functions of the system.

crucial short time-to-market constraints that becomes essential for the success or failure of system under development.

power consumption constraints which are always substantial for battery-operated systems.

low-cost constraints decides the viability of system.

endless pressure for increasing functionalities.

..

The above mentioned and many other design constraints play a key role in the immense growth of system complexity. One way of dealing with such complexities is with the help of system models at numerous levels of abstraction such that only specific complexity aspect can be visualized in a graphical manner. In this way, designers with unique expertise relevent for a particular system aspect can be employed to deal with such complexities. System complexity applies both to application and platform aspects. The difficulties come especially in the stage of application mapping and allocation, in the context of multiprocessing, considering also specifics of the platform.

Another way of dealing with complexities is with the use of models and model-based development (MBD) (briefly elaborated in Chapter 2). The word ‘model’ refers to describe something with simplicity. Here, simplicity refers to hide out those details which are less important pertaining to a certain concern, but the less important details here could be important ones in other models when concerns change. The process of building models is called modeling. At the moment, modeling performs a significant role in systems engineering (especially core software systems). The modeling process is based on divide-and-conquer approach where we can limit our focus in models over certain aspects of the system-under-development. Different members with specific expertise from the development team then concentrate on particular aspects of the system and provide solution in a quick manner. This brings us to our definition of the term ‘model-based development’ which we follow in this thesis because there can be numerous interpretation of this generic term. Model-based development or MBD is a development approach with the use of models which are specified in a particular domain specific language related to specific application domain for different activities in a design process. MBD is a usual approach being immensely used in different application domains [51][52] to minimize development efforts and time.

PO - performance optimization. It is an important, and most of the times a primary challenge of an embedded system design. In recent years, it has got foremost attention especially in the digital signal processing (DSP) applications. Consequently, it plays a major player in increasing CoD, and hence, new multiprocessing architectures has been introduced to deal with CoD and PO. An intelligent mapping of application functions on the multiprocessing architectures is the key to exploit tremendous features (including performance) from such architectures. A bad mapping mostly makes the chosen architecture worthless and unnessary waste of certain cost(s).

In our approach for PO, various mapping and allocation scenarios will provide different performance results, given the inter task communication requirements both at application and at platform levels.

CoPE - correctness of platform execution. This deals with the proper ordering of application tasks after allocation, considering the support for parallelism.

DE - designer expertise. Following CoD, experienced developers may be required in the process, possessing detailed knowledge about platform characteristics and how issues may be solved at platform levels.

4 Thesis Approach and Contributions

This thesis presents our approach to addressing the previously mentioned challenges. The thesis presents a model-based development and verification framework for embedded systems in general, and MPSoC in particular. As mentioned earlier, the particular MPSoC platform we consider for this thesis is the SegBus platform. From a high-level perspective, the key contributions of this thesis are structured around the following directions.

HLDE - high level design entry. We use the Unified Modeling Language (UML) as a high level design point for illustrating both the platform (SegBus) characteristics and to support the allocation and mapping of application tasks. We see choice as addressing the CoD, CoPE and DE challenges, while also providing the necessary support for the solutions detailed below.

PE - platform emulation. Emulation is used here to provide estimative results prior to having an actual implementation of the application on the platform. This is an important step in observing at early design stages the quality and performance of a design. Addresses PO, CoPE and DE.

ACG - automatic code generation. A general solution to address CoD and DE. In the present context, it also addresses CoPE.

The Unified Modeling Language (UML) [54] has been utilized in novel design methods proposing a solution for the challenges in the design flow of electronic systems. Here, the purpose is to provide a unitary environment for platform modeling, application mapping and system emulation, such that performance is estimated and adjusted to optimal levels in a correct and fast manner. The key contributions of this thesis are listed below.

1. We introduce, in this thesis, a model-based development (MBD) support for SegBus design. The choice of MBD helps us address CoD (by HLDE), CoPE (support for structured design, and correctness related aspects - customization classes, OCL constraints, etc, support for design reuse - library). Not in the least, it addresses DE, as a hardware non-specialist (such as a software designer) may also develop applications not being fully aware of the specifics of the underlying hardware platform.

We then present a technique to setup a graphical interface (GI) in the form of SegBus DSL in an existing modeling tool [49] to get as much advantage of pre-existing modeling infrastructure for the analysis of various SegBus instances that may answer to specific application requirements. The customization for each platform instance is defined in the form of user-defined rules. These customization rules set properties on each profile element about their relationships, ownerships, etc. The customization rules impose restrictions on profile elements during application / platform modeling, in order to provide a structurally correct version of the platform instance.

The GI answers especially the CoD and CoPE challenges, providing the HLDE solution. By including model validation features, the GI also serves the DE challenge.

2. We develop an emulator program targeting the SegBus platform as part of the framework to perform emulation on the modeled configuration in DSL. A code generation engine transforms the platform-independent and platform-dependent models of application, as modeled in DSL, into XML schemes. The generated XML schemes are then employed by the emulator program to estimate the utilization of platform elements with respect to data transfers and total execution time. After the analysis of the returned results, the designer is able to take decisions on whether the emulated configuration is the best/optimal or not for the target application, and can change the platform configuration before moving towards lower levels of the design process.

Hence, the realization of the emulator addresses, via PE the PO, CoPE and DE challenges.

3. We present methods to generate application’s execution schedule from system models which later to be used by the platform’s arbiters. Such capability is developed within the emulator program. If we find the performance aspects from the emulated system at an optimum/best level, we can generate the "application dependent" transaction-level control code based on VHDL, in an automated manner.

Hence, with this technique, we addresses the ACG and DE challenges via GI and PE.

5 Related Work

As we discussed in section 1, the design methodologies and frameworks being used today for embedded systems development lacks automation in various stages of their design process. We have gone through several research studies where the authors present concepts in some particular area of the design process, as our proposed framework deals with. For instance, few studies we have come across deal with high-level modeling of the embedded systems while others express ideas specifically for system emulation. Following we show few studies which are similar to our proposed framework up to some extent.

The UML Profile for MARTE [58] has been standardized by OMG few years ago. As the name suggests, MARTE profile is intended for the modeling and analysis of real-time and embedded systems in a generic way. The profile consists of various packages and notations, which help to specify and validate target systems on a number of abstraction levels. Besides all its notations, MARTE does not provide certain methodology for designing concerned systems (real-time and embedded). The methodology gets prime focus when the design efforts are targeted significantly, from very beginning, for a particular platform (SegBus platform in our case). Gamatié et al. [59] introduced Gaspard framework for designing massively parallel embedded systems. The framework is based on MARTE profile where system is defined initially, and refined in a step-by-step manner for final implementation. Since the framework does not target any specific platform (unlike our approach), therefore it provides opportunities for early design space exploration to get optimum solution for implementation. The refinements in their framework are based on model-driven principles similar to our approach. Moreover, Architecture Analysis & Design Language (AADL), standardized by SAE International [60], is a modeling language for software-intensive system, which has gained popularity from industries of mission-critical systems in recent years. However, the issues highlighted in [61] pertaining to the weaknesses in the usability of AADL makes it inappropriate for our framework.

Kangas et al. [16] introduced a UML-based framework named as Koski for the MPSoC design and implementation. Koski provides tools ranges from application modeling to architecture implementation. The framework is based on a custom UML profile (the TUT profile) similar to our work. The framework also supports synthesis and automated design space exploration for deciding the right architecture for the target application, but their approach does not consider a definite architecture/platform for application implementation, as our work is focused on the SegBus platform. Another difference compared to our approach, they do not employ MDA and package-based communication in their approach as we do since the communication is a proven overhead for MPSoC systems being developed nowadays. However, in a sense, their design flow seems got inspired by the MDA viewpoints.

R. Thomson et al. [38] developed and implemented a H.264 decoder unit in an UML environment, exposing models for both hardware and software components. The FalconML tool is used to model different aspects of the applications via various UML diagrams, and the flow offers eventually RTL level code (VHDL) which can be used to synthesize the design. The difference to our approach here is that we already have a target platform for implementation.

Many DSLs have been proposed targetting a variety of application domains as we consider SegBus platform as our target domain. Consel et al. [25] introduced the Spidle - DSL for specifying streaming applications, with a compiler for generating source code. The approach was validated experimentally by comparing source code generated by Spidle compiler with an equivalent C source code. A number of optimizations in Spidle compiler are missing, such as locality in data and instruction caches, performance impact of buffering input streams, etc. Similarly, Arora et al. [24] presented a DSL for introducing application-level Checkpointing and Restart (CaR) mechanism in legacy applications for dynamic and distributed environments. The idea is to make sequential and parallel legacy system to be fault-tolerant by introducing code for CaR mechanism in high-level specifications.

Riccobene et al. [42] presented a UML profile for SystemC and defined a language to specify, analyze, design, and visualize artifacts in a SoC design flow. The profile provides a modeling framework for systems in which high-level models can be refined down to an implementation language. However, the work concluded that there is still a need to develop appropriate mechanisms and tools to fully utilize UML-based profiles system development with automation support. Unlikely, we develop a comprehensive UML-based profile for the SegBus platform embedding structural semantics in a graphical form while imposing restrictions among graphical elements at the same time.

Furthermore, the primary objective while designing emulator applications is to get as much as possible accuracy in estimating the execution results that we can expect from the real platform. Several research studies have been presented in recent years where the target was to achieve an emulation program for different hardware platforms, specially for the Network-on-Chip (NoC) [1], but there exists a number of emulation tools for other areas as well.

Schelle et al. [43] introduced an emulation tool - NoCem, for NoC exploration. The tool provides capability to emulate memory architectures, asymmetric processor configuration, special purpose offload, etc. The tool is able to deliver path latencies used for any particular transfer between processor cores and provides a true picture of the communication bottlenecks within the NoC platform quite similar to our approach of emulation in the framework.

Liu et al. [32] presented NoCOP - an emulation and verification framework for exploring the on-chip interconnection architecture. An instruction-set simulator and universal serial bus communicator has also been introduced to set the parameters for the emulation environment. Through the experimental results using both software and hardware, the authors proved that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy and decrease the usage of the resources of the Field Programmable Gate Array (FPGA). The design under emulation needs to be programmed onto a FPGA device and a separate host computer is responsible for initializing and managing emulation of the programmed design in the FPGA which makes it less flexible compared to our approach which is more flexible and does not require any FPGA device and consideration about deeper levels of abstraction in the early stages of the design process.

Genko et al. [17] presented a NoC emulation platform implemented on FPGA. The NoC hardware platform has been implemented on a Virtex-II FPGA, which consists of network injection, reception and controller components. The integrated PowerPC processor core functions as a controller. Instead of merely being the platform where the circuit is prototyped, the method can speed up functional validation and add flexibility to the NoC configuration exploration. The major drawback in their approach is the use of processor core in the hardware to control and monitor the network at the cost of FPGA resources, already limited.

MDA has been utilized in different design areas to provide automation up to some extent. MDA facilitates us to specify a system in various facets, also known as models. With the refinement techniques, one can figure out ultimately a complete system with the help provided transformation techniques (Model-to-Model, Model-to-Text, etc.) applied to different models. Below we list few studies where authors employ MDA in the embedded system development at different abstraction levels.

Vidmantas et al. [19] introduced MDA methods where the designer can model "Platform Independent Model" (PIM) of a application using UML together with SysML plug-in. They introduced techniques to transform PIM into PSM model, which is later transformed into source code specifically for one operating system (OS), similar to our approach where we generate execution schedule to be used by the arbiters of the platform. The authors have considered more than one OS where the modeled application can be run, unlike our case where there is no consideration of OS is required.

Koudri et al. [28] presented a design flow for System-on-Chip / System-on-Programmable Chip design based on the use of UML and dedicated profiles. They supported the use of the Model-Driven Development (MDD) for the hardware-software co-design with an example of Cognitive Radio Application, implemented on FPGA. The modeling tool they used generates thousands of lines of code for the modeled example application but further improvements needs to be done, particularly in the Model of Computations support.

M. Thompson et al. proposed a highly automated framework titled as Daedalus for system-level architectural exploration, system-level synthesis, programming and prototyping of heterogeneous MPSoC platforms [36][37]. Their framework allows to construct customizable MPSoCs platforms from a library of pre-defined and pre-verified IP components, similar in an aspect to our approach of having a library of pre-built functional components, but dissimilar in another aspect where we already have a platform - the SegBus.

6 Thesis Organization

The remainder of this thesis is organized as follows. In Chapter 2, we provide a short description of the SegBus platform with its structural characteristics. Next, in Chapter 3, we discuss our design methodology that employs the proposed model-based framework while designing applications targeting the SegBus platform. The development of the SegBus DSL and the associated library of reusable components are described in Chapter 4. The approach of emulating and estimating the modeled system is presented in Chapter 5, while the method of execution schedule generation from the modeled system is briefly discussed in Chapter 6. Furthermore, in Chapter 7, we formally employ and validate the proposed framework on a real application as an example, followed by a discussion of the proposed framework. Finally, we conclude the thesis in Chapter 8.

7 Thesis Navigation

Figure 2: Navigation of the dissertation.