Simulation Deals With The Implementation Of Recovery Computer Science Essay

Published Date: 02 Nov 2017

1 SARAH BOBBINA KURIEN,2 Prof.P.K. Sakthivel

1P.G Scholar, 2 Assosciate professor, Head of the Department

Department of Electronics &Communication Engineering,

GnanamaniI College Of Technology, Namakkal - 637 018

1 [email protected], [email protected]

Abstract- This project design and simulation deals with the implementation of Recovery Boosting technique in Schmitt-Trigger (ST)-based differential-

sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. Recovery Boosting provides significant improvement in the static noise margins of the register file and issue queue while having very little impact on power consumption and performance. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance. The performance of proposed system was analysed through simulations with MICROWIND/DSCH software.

KEYWORDS - Low-voltage SRAM, process tolerance, Schmitt- Trigger (ST), Negative bias temperature instability (NBTI).

I. INTRODUCTION

P ORTABLE electronic devices have extremely low power requirement to maximize the battery lifetime. Various device-/circuit-/architectural-level

techniques have been implemented to minimize the power consumption . Supply

voltage scaling has significant impact on the overall power dissipation. With the supply voltage reduction, the dynamic power reduces quadratically while the leakage power reduces linearly. However, as the supply voltage is reduced, the sensitivity of circuit parameters to process variations increases. This limits the circuit operation in the low-voltage regime, particularly for SRAM bitcells employing minimum-sized transistors. These minimum geometry transistors are vulnerable to interdie as well as intradie process variations. Intradie process variations include random dopant fluctuation (RDF) and line edge roughness (LER). This may result in the threshold voltage mismatch between the adjacent transistors in a memory bitcell, resulting in asymmetrical characteristics . The combined effect of the lower supply voltage along with the increased process variations may lead to increased memory failures such as read-failure, hold-failure, write-failure, and access-time failure.

One important hard error phenomenon is negative bias temperature instability (NBTI), which affects the lifetime of pMOS transistors. NBTI occurs when a negative bias (i.e., a logic input of "0") is applied at the gate of a pMOS transistor. The negative bias can lead to the generation of interface traps at the . interface, which cause an increase in the threshold voltage of the device. This increase in the threshold voltage degrades the speed of the device and reduces the noise margin of the circuit, eventually causing the circuit to fail . One interesting aspect of NBTI is that some of the interface traps can be eliminated by applying a logic input of "1" at the gate of the pMOS device. This puts the device into what is known as the recovery mode, which has a "self-healing" effect on the device .

Memory arrays that use static random access memory (SRAM) cells are especially susceptible to NBTI. SRAM cells consist of cross-coupled inverters that contain pMOS devices. Since each memory cell stores either a "0" or a "1" at all times, one of the pMOS devices in each cell always has a logic input of "0." Since modern processor cores are composed of several critical SRAM-based structures, such as the register file and the issue queue, it is important to mitigate the impact of NBTI on these structures to maximize their lifetimes.

. However, one of the devices is always in the negative bias condition at any given time. In this paper, we propose a novel technique called Recovery Boosting that allows both pMOS devices in the memory cell to be put into the recovery mode. The basic idea is to raise the ground voltage and the bitlines to when the cell does not contain valid data.

II. PROPOSED SYSTEM

The main circuit of the proposed Schmitt-Trigger based SRAM cell with Recovery Boosting system is shown in figure 1.In order to resolve the conflicting read versus write design requirements in the conventional 6T bitcell, we apply the Schmitt Trigger (ST) principle for the cross-coupled inverter pair. A Schmitt trigger is used to modulate the switching threshold of an inverter depending on the direction of the input transition . In the proposed ST SRAM bitcells, the feedback mechanism is used only in the pull-down path, as shown in Fig. 2. During0→1 input transition, the feedback transistor (NF) tries to preserve the logic "1" at output (Vout ) node by raising the source voltage of pull-down nMOS (N1). This results in higher switching threshold of the inverter with very sharp transfer characteristics. Since a read-failure is initiated by a0→1 input transition for the inverter storing logic "1," higher switching threshold with sharp transfer characteristics of the Schmitt trigger gives robust read operation.

For the1→0 input transition, the feedback mechanism is not present. This results in smooth transfer characteristics that are essential for easy write operation. Thus, input-dependent transfer characteristics of the Schmitt trigger improves bot read-stability as well as write-ability of the SRAM bitcell. Two novel bitcell designs are proposed. The first ST-based SRAM bitcell is termed the "ST-1" bitcell while the other ST bitcell is termed the "ST-2" bitcell.

The cross-coupled inverters store one bit of data. There are three basic operations that one can perform on this SRAM cell: read, write and hold. To read and write data, the cell is selected by raising WL to high. This activates the access transistors and connects the inverters in the cell to the bitlines. During a read operation, both bitlines are first precharged high. Based on the data stored in the cell, one of the bitlines is discharged.

This change is detected by a sense amplifier (which is not part of the cell) to determine the value stored in the cell. During a write operation, one of the bitlines is raised high and the other is lowered depending on the value to be written to the cell. When the cell is not selected(WL=0) for read or write, it is expected to hold the data stored in it and is said to operate in the hold mode. Since the SRAM cell has cross-coupled inverters, each inverter charges the gate of the pMOS or nMOS device of then other inverter. Therefore, at any given time, one pMOS device will always be in the stress mode. The goal of recovery enhancement is to put the pMOS devices into the recovery mode by feeding input values to the cell that will transition them into that mode. However, due to the cross-coupled nature of the inverters, only one of the pMOS devices can be put into the recovery mode.

. NBTI occurs when a negative bias (i.e., a logic input of "0") is applied at the gate of a pMOS transistor. The negative bias can lead to the generation of interface traps at the . interface, which cause an increase in the threshold voltage of the device. This increase in the threshold voltage degrades the speed of the device and reduces the noise margin of the circuit, eventually causing the circuit to fail . One interesting aspect of NBTI is that some of the interface traps can be eliminated by applying a logic input of "1" at the gate of the pMOS device. This puts the device into what is known as the recovery mode, which has a "self-healing" effect on the device .

When silicon is oxidized, most of the Si atoms at the surface of the wafer bond with oxygen while a few atoms bond with hydrogen. When a negative bias (i.e., a logic input of "0") is applied at the gate of a pMOS transistor(Vgs=-Vdd) , the relatively weak Si-H bonds get disassociated, leading to the generation

of interface traps at the Si/SiO interface. These interface traps cause the threshold voltage of the pMOS transistor to increase, which in turn degrades the speed of the device.

The basic idea behind recovery boosting is to raise the node voltages (Node0 and Node1 in Fig. 1) of a memory cell in order to put both pMOS devices into the recovery mode. This can be achieved by raising the ground voltage to the nominal voltage through an external control signal. The modified SRAM cell has the ground connected to the output of an inverter. CRis the control signal to switch between the recovery boost mode and the normal operating mode. During the normal operating mode, CR has a value of "1" (Vdd), which in turn connects the ground of the SRAM cell to a value of "0." With this connection, the SRAM cell can perform normal read, write, and hold operations.

To apply recovery boosting, CR has to be changed to a "0" in order to raise the ground voltage of the SRAM cell toVdd . This circuit configuration puts both pMOS devices in the SRAM cell into the recovery mode. A cell can be put into the recovery boost mode regardless of whether its wordline (WL) is high or low. Unlike read and write operations on a cell, putting a cell into the recovery boost mode does not require an access to its wordline.

To achieve a good SNM, it is important to minimize the increasein due to NBTI of both pMOS devices in the memory cell. Additionally, it is also important to ensure that the difference in the threshold voltages between the two pMOS devices is kept as small as possible. Recovery Boosting addresses the first condition whereas Balancing addresses the second. one of the pMOS devices in each memory cell stays in the stress phase while the other in the recovery phase. This increases the difference in the between the two pMOS devices and therefore degrades the SNM.

Fig 1 Schmitt-trigger based SRAM cell with Recovery Boosting system

Fig 2 ST-1 BIT CELL

A ST-1 BIT CELL

The ST-1 bitcell utilizes differential sensing with ten transistors, one word-line (WL), and two bitlines (BL/BR). Transistors PL-NL1-NL2-NFL form one ST inverter while PR-NR1-NR2-NFR form another ST inverter Fig. 2 shows the schematics of the ST-1 bitcell.. Feedback transistors NFL/NFR raise the switching threshold of the inverter during the input transition giving the ST action.

Fig 3 ST-2 BIT CEL

B. ST-2 Bitcell

ST-2 bitcell utilizing differential sensing with ten transistors, two word-lines (WL/WWL), and two bitlines (BL/BR). The WL signal is asserted during read as well as the write operation, while WWL signal is asserted during the write operation. Fig. 3 shows the schematics of the ST-2 bitcell. During the hold-mode, both WL and WWL are OFF. In the ST-2 bitcell, feedback is provided by separate control signal (WL) unlike the ST-1 bitcell, where in feedback is provided by the internal nodes. In the ST-1 bitcell, the feedback mechanism is effective as long as the storage node voltages are maintained.

Once the storage nodes start transitioning from one state to another state, the feedback mechanism is lost. To improve the feedback mechanism, separate control signal WL is employed for achieving stronger feedback.

III. CONCLUSION AND FUTURE WORK

A Schmitt trigger based fully differential, robust, 10 transistor SRAM bitcell suitable for sub-threshold operation.. It incorporates fully differential operation and hence it does not require any architectural changes from the present 6T architecture. At iso-area, the proposed ST bitcell operates at a lower VDD with lower leakage and reduced read/write power. Simulation results show that the ST bitcell can also reduce rms noise compare with other 10T SRAM cell .in future we will reduce the NBTI problem from ST SRAM cell .

we knowNegative bias temperature instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAMbased structures within the processor are especially susceptible to NBTI since one of the pMOS devices in the memory cell always has an input of "0". Previously proposed recovery techniques for SRAM cells aim to balance the degradation of the two pMOS devices by attempting to keep their inputs at a logic "0" exactly 50% of the time. However, one of the devices is always in the negative bias condition at any given time. In this paper, we propose a technique called Recovery Boosting that allows both pMOS devices in the memory cell to be put into the recovery mode by slightly modifying to the design of conventional SRAMcell