Removal Of Impulse Noise In Images Computer Science Essay

Published Date: 02 Nov 2017

X. Jushwanth Xavier

M.E Student,

Velammal Engineering College,

Chennai, India,

[email protected]

Benujah B.R

M.Tech Student,

Regional Centre of Anna University Tirunelveli, Tirunelveli, India,

[email protected]

ABSTRACT

During the process of signal acquisition and transmission images or frames of the transmitted data may be affected by impulse noise. In this paper, an efficient way of removing impulse noise is presented. The method used here focus on the VLSI methodology to reduce noise present in image by preserving the edge. Simulation results show that the proposed technique provides an efficient method in preserves the edge features and obtains excellent performances in terms of visual quality. The design requires only low computational complexity and small memory buffers. Its hardware cost is quite low. Our design achieved better visual quality with reduced area.

Keywords

Edge preservation, impulse noise, EPT, VLSI

Introduction

In image and video applications such medical imaging, image segmentation, and face recognition systems images are corrupted by noise during the process of image acquisition and even during transmission. This leads to the failure of many image based applications. Hence, an efficient de-noising technique is required for the image processing applications [1]. Recently, many image de-noising methods have been developed to carry out the impulse noise suppression [2]–[7]. Some of them employ the median filter [2] or its modifications [3], [4] to implement de-noising process. However, these approaches may blur the image since noise-free pixels are modified. To avoid the damage on noise-free pixels, an efficient switching strategy has been proposed in the literature [5]–[7]. In general, the switching median filter [5] consists of two steps:

1) Impulse detection

2) Noise filtering.

It locates the noisy pixels with impulse detector and filters them rather than the whole pixels in an image to avoid the damage on noise-free pixels. Generally, the de-noising methods used for impulse noise suppression can be classified as:

lower-complexity [6]–[13]

Higher-complexity [14]–[17].

The former uses a fixed-size local window and requires a few line buffers. And its computational complexity is low and can be comparable to median filter or its modification [2]–[4]. The latter yields visually pleasing images by enlarging local window size adaptively [15], [16] or doing iterations [14]–[17].

In this paper, we focus only on the lower-complexity de-noising techniques for image and videos because of its simplicity and easy implementation with the VLSI circuit. In [6], new impulse detector (NID) for switching median filter is proposed. NID that uses the minimum absolute method four convolutions are obtained by using Laplacian 1-D operators to detect noisy pixels. Differential rank impulse detector (DRID) is discussed in [7]. The impulse detector that is used in DRID is based on a comparison operation of signal samples within a narrow window based on ranking absolute value. Efficiently remove the impulse noise (ERIN) In [8], which can based on simple fuzzy impulse detection technique. An alpha-trimmed mean -based method (ATMBM) the operations is discussed in [9]. here a decision-based algorithm (DBA) is proposed to remove the corrupted image by the median or by its neighbouring pixel value. For real-time embedded applications implementing of switching median filter removal of impulse noise is necessary and should be considered. In consumer products the cost and efficiency plays a major role. We hope to focus on low-cost de-noising implementation in this paper. The cost of VLSI implementation depends mainly on the size of the memory and computational complexity. Hence, small memory and operations are necessary for a low-cost, low complexity de-noising implementation. Based on these two factors, we propose an Edge preservation technique (EPT) and its VLSI implementation for removing fixed-value impulse noise (salt and pepper noise). The storage space needed for EPT is two line buffers rather than a full frame buffer. Only simple arithmetic operations, such as addition and subtraction, are used in EPT which directly operate on the noisy pixels depending on the neighbours. We proposed a impulse noise detector to detect noisy pixel and an effective design to locate the edge of it. The experimental results demonstrate that EPT can obtain better performances in terms of both quantitative evaluation and visual quality than other methods that belongs to the same category of lower-complexity impulse de-noising methods [6]–[13]. Further, the VLSI implementation also outperforms previous methods described in [11]–[13], [19], [20] in terms of quantitative evaluation, visual quality, and hardware cost.

PROPOSED METHOD

Assume that the current pixel to be de-noised is located at coordinate (i,j) and denoted as pi,j , and its luminance values of the pixels before and after the de-noising are represented as fi,j and i,j, respectively. If pi,j is corrupted by the fixed-value impulse noise, its luminance value will jump to be the minor max value in gray scale. Here, we adopt a 3x3 mask centering on pi,j for image de-noising. In the current W , we know that the three de-noised values at coordinates (i-1,j-1) , (i-1,j) and (i-1,j+1) are determined at the previous de-noising process, and the six pixels at coordinates(i,j-1), (i,j) , (i,j+1),(i+1,j-1), (i+1,j), and (i+1,j+1) are not de-noised yet, as shown in Fig. 1.

Fig 1: 3 x 3 Mask

A pipelined hardware architecture is adopted in the design, so we assume that the de-noised value of pi,j-1 is still in the pipeline and not available. Using the 3 x 3 values in, EPT will determine whether pi,j is a noisy pixel or a noise free pixel. If there is any error, EPT locates the directional edge that exists in and uses it to determine the reconstruction of image.

EPT is composed of three components: extreme data detector, edge-oriented noise filter and impulse arbiter. The extreme data detector detects the min and max luminance values of pixels in W, and determines whether the luminance values of pi,j and its five neighbouring values are equal to the extreme data. By observing spatial correlation between values the edge-oriented noise filter points a directional edge and generates the estimated value of current pixel. Finally, the impulse arbiter brings out the proper result.

A. Extreme Data Detector

The extreme data detector detects the min and max luminance values (MIN W and MAX W) in those processed masks starting from the first one to the current pixel of the image. If a pixel is corrupted by the impulse noise of fixed value, its luminance value will jump to be the min or max value in gray scale. If fi,j is not equal to MIN W and MAX W, we conclude that pi,j is a noise-free pixel and the following steps for de-noising are skipped. If fi,j is equal to MIN W or MAX W , we set φ to 1, check its five neighbouring pixels values are equal to the extreme data and store the compared binary results into B

B. Edge-Oriented Noise Filter

To locate the edges that existed in W, a simple edge catching technique can be realized easily with the help of VLSI circuit is adopted. To decide the edge, we consider 12 directions, from D1 to D2, as shown in Fig. 2. Only the noise-free pixels are taken into account in order to avoid possible misdetection of the edges. If a bit B is set to a value equal to 1, it means that the pixel is related to the binary flag and suspected to be a noisy Pixel. Directions passing through this suspected pixel are discarded in order to reduce misdetection. In each condition, at most four directions are chosen this will reduce the hardware complexity. If there appear more than four directions, only four are chose according to the variation in angle with respect to the noise free pixels. Fig. 3 shows the mapping table between B and the chosen directions adopted in the design.

Fig 2: EPT edge patterns

Different edge patterns are developed as shown in figure 2 and the binary values are assigned to determine the edges.

C. Impulse Arbiter

Since the value of the image pixels are corrupted by the fixed-value impulse noise will jump to be the min/max value in gray scale, we can conclude that if pi,j is corrupted, fi,j is equal to MIN W or MAX W. However, the converse is not true. If fi,j is equal to MIN W or MAX W. pi,j may be corrupted in the region with the highest or lowest luminance values. In other words, a pixel whose value is MIN W or MAX W might be identified as a noisy pixel even if it is not corrupted. In order to overcome this drawback, we add another possible condition to reduce the possibility of misdetection. If pi,j is a noise-free pixel and the current mask has high spatial correlation, that is very close to pi,j and is small. That is to say, pi,j might be a noise-free pixel but the pixel value is or if is small. Hence an efficient method to provide smart deduction is to use threshold values hence a threshold value that is near to the luminance and the pixel values are selected to overcome misdetection.

VLSI IMPLEMENTATION OF EPT

EPT is low computational complexity and requires only two line buffer, hence the cost of VLSI implementation is low compared to the previous methods. In order to reduce the timing delays, the pipelined architecture is

Fig 3: VLSI architecture for EPT.

adopted which can produce an output at every clock cycle. According to our simulation results, we found the access time required for SRAM is near to 6 ns. Since the operation of SRAM access belongs to the first pipeline stage, we divide the remaining steps into 6 stages so that the propagation delay of each stage remains the same 6ns . The architecture consists of five main blocks: line buffer, register bank, extreme data detector, edge-oriented noise filter and impulse arbiter. Each of them is described briefly in the following subsections.

A. Line Buffer

EPT adopts a 3 x 3 mask, so three scanning lines are

needed. If pi,j are processed, three pixels from rowi-1, rowi and rowi+1, are needed to perform the de-noising

Fig 4: register bank of EPT

process. With the help of four crossover multiplexers we realize three scanning lines that are connected with two line buffers. As shown in Fig. 5, Line Buffer-odd and Line Buffer-even are designed in such a way to store the pixels at odd and even positions, respectively.

the line buffer is implemented with a dual-port SRAM to resuce the (one port for reading out data and the other port for writing back data concurrently) instead of a series of shifter registers.

Fig 5: interconnections between two line buffers and RB

represents the number of pixels stored in the register bank.

B. Register Bank

The register bank (RB), consisting of 9 registers, is used to store the 3 x 3 pixel values of the current W mask . Fig. 6 shows its architecture where each 3 registers are connected serially in a chain to provide three pixel values of a row in W, and Reg4 keeps the luminance value of the current pixel to be de-noised. Obviously, the de-noising process for pi,j does not start until it enterers from the input device. The nine values stored in RB are then used simultaneously by subsequent extreme data detector and noise filter for de-noising.

Once the de-noising process for pi,j is completed, the reconstructed pixel value is generated by the arbiter is outputted and written into the line buffer storing rowi to replace fi,j .

When the de-noising process shifts from pi,j to pi,j+1 , only 3 new values are needed to be read into RB (Reg2, Reg5 and Reg8, respectively) and other 6 pixel values are shifted to each one’s proper register. At the same time, the previous value in Reg8 is written back to the line buffer storing for subsequent de-noising process.

The selection signals of the four multiplexers are all set to 1 or 0 for de-noising the odd or the even rows, respectively. Two examples are shown in Fig. 7 to illustrate the interconnections between the two line buffers and RB. Assume that we de-noise row2, and set all four selection signals to 0, those samples of row1 and row2 are stored in Line Buffer-odd and Buffer-even, respectively. The samples of row3 are inputted from the input device, as shown in Fig. 7(a). The previous value in Reg8 and the de-noised results generated by the arbiter are written back to Line Buffer-odd and Line Buffer-even, respectively. After the de-noising process of row2 has been completed, Line Buffer-odd is now full with the whole samples of row3, while those de-noised samples of row2 are all stored in Line Buffer-even. To de-noise row3, we set all selections signals to 1. Thus the previous value in Reg8 and the de-noised results generated by the arbiter are written back to Line Buffer-even and Line Buffer-odd, respectively, as shown in Fig. 7(b). After the de-noising process of row3 has been completed, Line Buffer-even is now full with the whole samples of row4, while those de-noised samples of row3 are stored in Line Buffer-odd.

C. Extreme Data Detector

Fig. 8 shows the 3-stage pipeline architecture of the extreme data detector in which P represents the pipeline register and EC is the equality comparator that will output logic 1 if both two input values are identical. The 2-stage min-max tree module is used to find MIN W and MAX W. Two columns of EC units are used to determine whether the lower six pixels in Wʹ are equal to MIN W or MAX W, respectively. Wʹ represents the eight neighbouring pixels’ values of pi,j in W. The six OR gates are employed to generate the binary comparison results and b1 - b5. When φ=0, it means pi,j is a noise-free pixel and the following operations can be skipped. In this condition, we disable those registers storing b1 - b5 and Wʹ to avoid unnecessary power consumption.

D. Edge-Oriented Noise Filter

Fig. 9 shows the 2-stage pipeline architecture of the edge-oriented noise filter in which the |SUB| unit is used to output the absolute value of difference of two inputs. Using B from the detector, the mapping module

Fig. 6: Architecture of Edge oriented noise filter

implements the table shown in Fig. 4 to locate the four directions which are composed of noise-free pixels. Four directional differences are calculated with the four |SUB| units. Then the smallest one is determined by

using the minimum tree unit. After that, the mean luminance having small directional difference is multiplexed.

E. Impulse Arbiter

Fig. 10 shows the architecture of the impulse arbiter in which comparator CMP is used to output logic 1 if the upper input value is greater than the lower one. The final multiplexer is used to output generated by the noise filter when pi,j is corrupted, or fi,j when pi,j is noise-free.

Fig 7: Impulse Arbiter

IMPLEMENTATION OF EPT

In EPT 12 edges are considered as explained above but in the terms of the proposed method only three edges are considered as shown on the figure. The VLSI implementation of the proposed reduced method uses the same components as that of the EPT since the number of the edges is reduced the proposed method reduces the number of clock cycles compared to that of the previous method which obviously leads to the reduction of the power and the area of the system.

Fig 7: proposed edge patterns

To verify the characteristics and performances of de-noising algorithms, a number of simulations are carried out on the six well-known 256 x 256 8-bit gray-scale test images. In the simulations, images are corrupted by impulse noise (salt-and-pepper noise), where "salt" and "pepper" noise are with equal probability. Furthermore, a range of noise ratios that varies from about 10% to 90% with increments of 10% was tested. EPT is better but the proposed technique provided comparable performance too.

CONCLUSION

In this paper, an efficient VLSI implementation for impulse noise removal is presented. The experimental results obtained shows that our design achieves excellent performance in quantitative evaluation and visual quality, even though the noise ratio is as high as 90%. For real-time applications, a 7-stage pipeline architecture for EPT and a 5-stage pipeline architecture for REPT are also developed and implemented. As the outcome demonstrated, REPT outperforms other chips [11]–[13], [19], [20] with the lowest hardware cost. The architectures have been evaluated with monochromatic images, but they can be extended for working with RGB color images and videos.