Internal Registers Of The Cpu

Published Date: 02 Nov 2017

The control unit of the CPU consists of a small, high speed memory used to store temporary results and certain control information. The control unit directs the operation of input devices, output devices, ALU, main memory and secondary memory of a computer. It sends control signals to various parts of the computer. Main functions of the control unit can be summarized as follows.

In general, it performs the data processing operations with the aid of programs prepared by the users and sends control signals to various parts of the computer systems.

It gives commands to transfer data from the input device to the memory to arithmetic logic unit.

It also transfers the results from ALU to the memory and then to the output devices.

It stores the program in the memory.

It fetches the required instructions from the main storage and analyses each instruction and hence deduces what operation is to be performed (that is decoding of instructions)

Internal Registers of the CPU

In addition to the ALU and the control unit of the CPU, there are a number of internal registers that are used either as a pair or as a single unit. The main purpose of these registers is not only to store the control information of the computer operation but also to perform program execution.

Various types of the internal registers of the CPU are the following:

General purpose registers

Data registers

Address registers

Condition code registers

General purpose registers can be assigned to a variety of functions by the programmer. However they are mainly employed for data transfer operations. Data registers can be used only to hold data and cannot be employed in the calculation of an operand address. Various types of address registers of general purpose computer systems are the following:

Segment pointers

Index registers

Stack pointers

Control code registers are special purpose registers commonly employed for performing execution related instructions. Examples of the control code registers are as given.

Program counter (pc)

Instruction register

Memory address register

Memory buffer register

4.0 – Answer for Question 1

History of CPUs

Previously, UNIAC Computers Company had to be bodily rewired to do diverse tasks, which made these devices to be named "fixed-program computers." As the term "CPU" is normally described as a device for software (computer program) execution, the first devices that could correctly be named CPUs came with the arrival of the stored-program computer.

(Tim Hall 2009)

4.1 – CISC

In 1960s, one main problem with initial computers was that a program for one would not work on others. Computer firms discovered that their clients had few reasons to stay loyal to a specific brand, as the following computer they bought would not be compatible anyway. At that time, price and performance were typically the only considerations. In 1962, IBM attempted a new method to designing computers. The idea was to make whole family of computers that could all run the same program, but with different prices and performance. As customers’ requirements extended they could move up to better computers, and still keep all of their data, storage media and programs. Nearly all following computers included these innovations in some form. This is now named a "Complex Instruction Set Computer," or CISC.

(QuinStreet Inc 2013)

4.2 – Large Scale Integration

About 1971, very little computers might be achievable because of the first calculator and clock chips. Intel 4004 was the first microprocessor, produced by Intel and designed in 1971 for the Busicom Company which was designed calculator. Around 1972, Intel presented a microprocessor having a different construction: the 8008. The 8008 is the straight forebear of the current Core i7, although the opcode values are dissimilar, each instruction of the 8008's instruction set has a straight corresponding in the Intel Core i7's much larger instruction set.

(Margaret Rouse 2012)

intel_8008

(Intel 8008)

http://www.eui.upm.es/museo_virtual/4g/intel8008

4.3 – RISC

Around 1980s, the UC Berkeley and IBM researchers found that almost those interpreters and computer language compilers used only a little subset of the instructions of a CISC. Lots of the power of the CPU was just being unnoticed in real-world use. They understood that by creating the computer easier and less orthogonal, they could make it rapider and cheaper at once. They conceived a computer design called RISC, or Reduced Instruction Set Computers. RISCs mostly had greater numbers of registers, accessed by easier instructions, with a few instructions specifically to load and store data to memory. Finally was a very high speed with a very simple core CPU running.

(Margaret Rouse 2005)

1713

(AMD AM290000)

http://www.oldcpu.cz/CPU/AMD/29000/Am29000-16GC/1713

4.4 – Today CPU

Multi-threading

When the computer is running only a single program, its designs work best at before; though nearly all current operating systems allow the users to run multiple programs simultaneously. CPU requires expensive context switching to change over and do work on another program. In contrast, multi-threaded CPUs can handle instructions of the multiple programs at once.

(Martin McCarthy 1997)

Multi-core

CPU cores are normally on the same die from Multi-core CPUs. Both cores connected to each other via a shared Level 2 or Level 3 cache, an on-die crossbar switch, or an on-die bus. The interconnect components are shared by both CPU cores on the die to interface to the rest of the system and other processors. A front side bus interface may include in these components, DRAM interfaces with a memory controller, other processors link to a cache coherent, the southbridge and I/O devices link to a non-coherent. A single die that contains multiple CPU cores, which called multi-core or MPU (Micro-Processor Unit), have come into general usage for a single die.

(TechTerms 2010)

Core-i7-3740QM

(Intel Core i7-3840QM) http://www.gadgetfreak.gr

6.0 – Conclusion for Question 1

In conclusion, we can know that CPUs are changing rapidly by year-to-year. At 1960s, IBM companies invented a new design which was called CISC to make whole family of computers that could all run the same program. In 1970s, they succeeded to change computers into very small size due to the 1st calculator and clock chips. In 1980s, they conceived RISC to make CPUs rapider and cheaper at the same time. Finally by today, they computer researchers break through a new level again, they invented multi-core to run multiple programs simultaneously with a fast speed.

Before CPUs are used to do calculation only. By today, CPUs are frequently used in many fields. For examples, smartphones, laptops, desktops, tablets, and so on. These devices have a specific function to let users feel convenience and user friendly for its use.

From the beginning of a room size’s CPU to a little size of CPU, it is not hard to believe that we can have better life in our future with the high technologies which are changing day by day from today. Even though some people may afraid that we will lost healthy because technologies help us to do all the things, but I believe that we can get a balance between healthy and technology to have a better and advanced lives.

7.0 – Introduction for Question 2

We know that the central processing unit memory unit and I/O unit are the hardware components/modules of the computer. They work together with communicating each other and have paths for connecting the modules together. The collection of paths connecting the various modules is called the interconnection structure. The design of this interconnection structure will depend on the exchanges that must be made between modules. A group of wires, called bus is used to provide necessary signals for communication between modules.

Internal bus

Internal bus, also known as internal data bus, memory bus or system bus or front-Side-Bus, connects all the internal components of a computer, such as CPU and memory, to the motherboard. Internal data buses are also referred to as a local bus, because they are intended to connect to local devices. This bus is typically rather quick and is independent of the rest of the computer operations.

External bus

The external bus, or expansion bus, is made up of the electronic pathways that connect the different external devices, such as printer etc., to the computer.

8.0 – Answer for Question 2

Bus

A bus that connects major computer components/modules (CPU, memory, I/O) is called a system bus. The system bus is a set of conductors that connects the CPU, memory and I/O modules. Usually, the system bus is separated into three functional groups:

(PatKay 2013)

Data Bus

The data bus consists of 8, 16, 32 or more parallel signal lines. These lines are used to send data to memory and output ports, and to receive data from memory and input port. Therefore, data bus lines are bi-directional. This means that CPU can read data on these lines from memory or from a port, as well as send data out on these lines to a memory location or to a port. The data bus is connected in parallel to all peripherals. The communication between peripheral and CPU is activated by giving output enable pulse to the peripheral. Outputs of peripherals are floated when they are not in use.

(wiseGEEK 2013)

Address Bus

It is a unidirectional bus. The address bus consists of 16, 20, 24 or more parallel signal lines. On these lines the CPU sends out the address of the memory location or I/O port that is to be written to or read from. Here, the communication is one way, the address is send from CPU to memory and I/O port and hence these lines are unidirectional.

(Heath, Steve. 2002)

Control Bus

The control lines regulate the activity on the bus. The CPU sends signals on the control bus to enable the outputs of addressed memory devices or port devices.

Typical control bus signals are:

Memory Read () – causes data from the addressed location to be placed on the bus.

Memory Write () – causes data on the bus to be written into the addressed location.

I/O Read () – causes data from the addressed I/O port to be placed on the bus.

I/O Write – causes data on the bus to be output to the addressed I/O ports.

Bus Request (BR) – indicates that a module needs to gain control of the bus.

Bus Grant (BG) – indicates that a requesting module has been granted control of the bus.

Interrupt Request (INTR) – indicates that an interrupt is pending.

Clock (CLK) – used to synchronize operation

Reset – initialized all modules.

Interrupt Acknowledge (INTA) - acknowledges that the pending interrupt has been recognized.

Hold Acknowledge (HLDA) - Indicates that data have been accepted from or placed on the bus.

(B Govindarajalu 2004)

http://cnx.org/content/m29708/latest/graphics12.jpg

(Bus Interconnection Scheme)

http://cnx.org/content/m29708/latest/

http://cse.iitkgp.ac.in/pds/notes/img/computer.gif

(Bus Structure)

http://cse.iitkgp.ac.in/pds/notes/intro.html

8.1 – Single Bus Structure

Another way to represent the same bus connection scheme is shown in Fig. **. Here, address bus, data bus and control bus are shown by single bus called system bus. Hence such interconnection bus structure is called single bus structure.

https://encrypted-tbn3.gstatic.com/images?q=tbn:ANd9GcRxNu0OumDOsZL7JvMz8GcEaALvKP6_kYGBf_88hhRWIshkBXiV

(Single Bus Structure)

http://jaymut2009.hubpages.com/hub/Computer-Bus-Structure

In a single bus structure all units are connected to common bus called system bus. However, with single bus only two units can communicate with each other at a time. The bus control lines are used to arbitrate multiple requests for use of the bus. The main advantage of single bus structure is its low cost and its flexibility for attaching peripheral devices.

(A. P. Godse & D.A. Godse, 2009)

The complexity of bus control logic depends on the amount of translation needed between the system bus and CPU, the timing requirements, whether or not interrupt management is included and the size of the overall system. For a small system, control signals of the CPU could be used directly to reduce handshaking logic. Also, drivers and receivers would not be needed for the data and address lines. But large systems with several interfaces would need bus driver and receiver circuits connected to the bus in order to maintain adequate signal quality. In most of the processors, multiplexed address and data buses are used to reduce the number of pins.

During first part of bus cycle, address is present on this bus. Afterwards, the same bus is used for data transfer purpose. So latches are required to hold the address sent by the CPU initially. Interrupt priority management is optional in a system. It is not required in systems which use software priority management. The complex system includes hardware for managing the I/O interrupts to increase efficiency of a system. Many manufacturers have made priority management devices. Programmable interrupt controller (PIC) is the IC designed to fulfill the same task.

(Shiva, Sajjan G. 2000)

8.2 – Multiple Bus Structures

The performance of computer system suffers when large numbers of devices are connected to the bus. This is because of the two major reasons:

When more devices are connected to the common bus we need to share the bus among these devices. The sharing mechanism co-ordinates the use of bus to different devices. This co-ordination requires finite time called propagation delay. When control of the bus passes from one device to another frequently, these propagation delays are noticeable and affect the performance of computer system.

When the aggregate data transfer demand approaches the capacity of the bus, the bus may become a bottleneck. In such situations we have to increase the data rate of the bus or we have to use wider bus.

(Lily_j 2013)

Nowadays the data transfer rates for video controllers and network interfaces are growing rapidly. The need of high speed shared bus is impractical to satisfy with a single bus. Thus, most computer systems use the multiple buses. These buses have the hierarchical structure.

Fig. 13 shows two bus configurations. The traditional bus connection uses three buses: local bus, system bus and expanded bus. The high speed bus configuration uses high-speed bus along with the three buses used in the traditional bus connection. Here, cache controller is connected to high-speed bus. This bus supports connection to high-speed LANs, such as Fiber Distributed Data Interface (FDDI), video and graphics workstation controllers, as well as interface controllers to local peripheral buses including SCSI and P1394.