Error Detection And Correction Codes

Published Date: 02 Nov 2017

Abstract— Soft errors, occurs when a radiation particle hits the device and changes the logical value of a memory cell or register. As technology scales, radiation particles that create soft errors are more likely to affect more than 1bit when they impact a memory or electronic circuit. In order to tackle this issue, several design techniques are being used, which consider reliability as a key design parameter. Those based on redundancy, as Triple Modular Redundancy(TMR) and Hamming Codes, are especially popular, since they are quite straightforward to implement.

TMR is more appropriated for modules using single registers like in pipelines, control and data path circuits, while Hamming code is a better trade-off for groups of registers, such as register files, caches and embedded memories. However, this usually comes at a high cost, which many times is unfeasible for certain kinds of applications. Therefore, it is convenient to understand the structure and functionality of circuits in order take advantage of their inherent protection capabilities and therefore, minimize the extra redundancy.

The FIR filters are widely used, as they have good stability and can be easily designed to match a given response. This paper introduces optimizations for the use of Hamming Codes to protect generic FIR filter, to show that by knowing attributes of the design to protect, it is possible to reduce resource consumption and achieve an optimal design.

.IndexTerms— Single Event Upsets. Triple Modular Redundancy, Hamming Codes, FIR Filters.

Introduction:

Cosmic rays in the upper atmosphere produce secondary particles, including neutrons. The neutrons have a low interaction probability with the atmosphere, and significant numbers of energetic neutrons arrive at the earth’s surface. The relative number of neutrons in terrestrial environments continues to increase at low energies. Thus the soft-error rate problem on the ground is much more Affected. Since the early stages of microelectronics, radiation has been identified as a source of alteration

functionality of integrated circuits.

As the technology is steadily evolving and shrinking from generation to generation, the effects of a charged particle striking the silicon surface of an integrated circuit are getting more and more significant. Radiation effects can be divided into two categories, Single Event Effects (SEE) and Total Ionizing Dose (TID). Permanent damage of the transistor or device structure results from TID and from the Single Event Latchup (SEL), Single Event Gate Rupture (SEGR) and Single Event Burnout (SEB) subclasses of SEE. Single Event Transient (SET) and Single Event Upset (SEU), which cause temporary or transient errors, are the other subclasses of SEE Techniques for mitigation of these effects are addressed in.

When a particle hits the silicon, it loses its energy and transmits it to the silicon, causing a current burst. In the case of SEUs, these can randomly change the content of storage cells. To protect storage cells of integrated circuits from this phenomenon, several approaches may be followed. One is by technology hardening of memory cells and another one is by designing circuits able to detect an SEU event and act accordingly to prevent error propagation and guarantee full reliability in the system. Triple Modular Redundancy (TMR) and Error Detection and Correction Code (EDAC), like Hamming Codes, BCH Codes, Reed-Solomon Codes, TCM-Viterbi Coder, Reed Muller Codes are examples of such methods.

Filters are commonly used in digital communication systems for equalization, signal separation, noise reduction, etc. As communications are fundamental to space borne applications, such as satellites, unmanned missions, etc., digital filters play an important role in space systems. There are two main types of digital filters: the recursive and the non-recursive filters. They are referred as infinite impulse response (IIR) filters and finite impulse response (FIR) filters, respectively. The FIR filters are widely used, as they have good stability and can be easily designed to match a given response.

I. RELATED WORK

Some types of information require strong protection against errors, such as application software code, data structures, parameters, filters and look-up tables are very sensitive and any content alteration may end up with catastrophic errors. Software-based Hamming Codes can be used to improve the reliability of the most important sections of the memory. The hamming code implementation is composed of a combinational block responsible to code the data (encode block), extra bits in the word that indicate the parity (extra latches or flip-flops) and another combinational block responsible to decode the data (decode block).

Fig.1.Existing Hamming EDAC Protection approach

Hamming code is an error-detecting and error correcting binary code that satisfies the equation.

d+p+1≤ 2p

where d is the number of data bits and p is the number of parity bits.These codes have a minimum distance of three, which describes the number of different bits between two valid codewords, and thus they are capable of correcting all single errors within a block. This capability is defined as Single Error Correction (SEC). Syndrome decoding is especially suited for Hamming codes. In fact, the syndrome can be formed to act as a binary pointer to identify the error location. Hamming encoders and decoders perform specific combinational operations on the data in order to generate parity bits (in the case of encoders) and to correct errors (in the case of decoders).

A previous approach to protect FIR filters using Hamming codes consists in adding one encoder and one decoder before and after each register that is going to be protected in Fig. 1.

This way of using EDAC codes to protect the circuit incurs a bigger delay in the critical path with respect to the use of TMR, which will be discussed further in this paper. The area is obviously larger than in the case of the unprotected FIR, as additional registers are needed in each tap plus the combinational logic for the encoders and decoders, but for some implementations it is lower than in the case of TMR, as shown in the following sections. In the rest of the paper, alternative approaches to protect FIR filters with Hamming codes are presented.

II. PROPOSED TECHIQUES

In this section, several enhancements are proposed to reduce the number of encoders. These are based on the specific system knowledge of the FIR implementation, an approach that has been previously used to protect other circuits.

Hamming Single Encoder

One of these enhancements would be to remove the encoders from the delay line, as shown in Fig. 3, as they are only used if there are errors in the circuit and even in that situation, if only a single error is present in the register, it can still be corrected with the decoder at each stage. In summary, these additional encoders Fig.2. FIR filter protection with a single encoder. Fig.3. FIR filter protection with additional data protection.are useful only if we assume that a tap value will be hit by more than one SEU at different time instants, as it propagates through the delay line.

Fig.2. FIR filter protection with additional data protection

Additional Hamming Data Protection

A further improvement would be to use the output of each decoder to feed the data bits of the next register while the parity bits are taken directly from the previous stage, as shown in Fig. 4.This would allow recovering from multiple errors that occur in the data bits as long as they happen in different clock cycles. This is achieved without additional encoders.

Fig.3. FIR filter protection with additional data protection

Shared Hamming Decoder

A more sophisticated approach to reduce the complexity is shown in Fig. 5, where the Hamming decoder is broken apart yielding a syndrome calculator, an error locator and an error corrector. The syndrome is calculated through XOR operations of the data and parity bits. This should contain only zeros when there are no SEUs. When the data bits contain an SEU, then there will be 1’s in the syndrome for identifying the SEU position in the locator, using the syndrome information.

The locator sends out an error vector with the exact position of the bit-flip to the corrector. This uses the OR-combined syndrome as an enable to initiate with the received error vector the correction of the faulty bit.In this way, the locator logic is shared among all taps reducing overall complexity under the assumption that only one SEU per cycle will occur. Moreover, it allows recovering from multiple errors in the data bits in different clock cycles, as in the design of Fig. 3.

D. Exploiting Hamming Through Parallelism

Now a days, it is common to find systems where parallel FIR filter structures are used, as for instance in digital communication such as wireless LAN or Ethernet, where there are 2 or 4 parallel FIR filters, respectively (see Fig. 4). By unifying the data streams from all the channels and coding them as one, as depicted in Fig. 8, reduction is achieved in the parity bits since when doubling the data bits , the parity bits only increase by one. According to (2), when increasing the data bits from 8 to 16 or 32, the parity bits increase by 1 or 2, respectively. In such a case, it is possible to use the error vector from Fig. 5 instead of doubling or quadrupling it for 2 or 4 parallel FIR filters, respectively. This is done by using different enables for each data block. All the techniques proposed in this section optimize and

highlight the benefits of Hamming protection. However, Hamming codes have some drawbacks when they are compared with TMR. The main one is that for all proposed techniques, the decoder unit or the syndrome, locator and corrector are added to the critical path of the output, and therefore, it decreases the maximum operating frequency of the circuit.

Fig.4. Four parallel FIR filter with Hamming protection

III Single Event Upsets Simulation Tool:

Single Event Effects and in particular Single Event Upsets are of major concern when dealing with electronic designs that will suffer the consequences of a radiation environment. The main reason for the development of this tool: to be able to emulate SEUs, easily and in a useful controlled manner, while still in the simulation (HDL) stages of the IC design flow.

One of the main concerns about introducing SEUs in HDL simulations, is to be able to do it with independence of the particular design and in a non-intrusive way. The use of Perl as the main programming language of the tool, and Tcl/tk to interact with the simulator. On the other hand, the fact that the bit-flips were to be done while a design was being simulated, created a dependency with the simulation tool (Modelsim).

BLOCK DIAGRAM:

Fig.5. Simulation environment block diagram

Results:

Fig.6. Inputs for FIR filter with single Encoder

Fig.7. Outputs for FIR filter with single Encoder

Fig.8. Inputs for FIR filter with additional data protection

Fig.9. Outputs for FIR filter with additional data protection

Conclusion:

Different approaches to protect generic FIR filters using Hamming codes against single events have been presented and put in perspective for ASICs and FPGAs. It has been shown that through understanding the system, enhancements to the design can be carried out to provide effective protection in exchange of a small frequency penalty.

It has been proved that the Hamming shared decoder is the most competitive solution based on area cost and performance. For example, assuming an 8-bit, 11-tap design, the area savings of this approach range from 10.45% (ASICs) to 14.97% (FPGAs). Future work includes the research of FPGA-oriented solutions for fault tolerant digital filters and the consideration of power consumption as a metric for optimization, since it is a key factor in space applications.