Performance Comparison Of Multi Standard Receiver Computer Science Essay

Published Date: 02 Nov 2017

Mr. Shinde Jitendrakumar Namdeo

Pune, Maharashtra, India

[email protected]

Dr. S. K. Bodhe.

Director, BoSh Technology,

Maharashtra, India

[email protected]

Introduction

In the information era people are living in a society in which processing, flow and exchange of information are vital for their existence. Two major issues related to flow and exchanges of information are connectivity and wireless technology. On the one hand computers and internet provides connectivity and wireless brings mobility. The functioning of the information society is unpredictable without the use of computer, internet and wireless technology. In future they will merge into a unique system for communication access to information as well as their exchange and processing. Network technologies are traditionally based on wireline but next generation is of wireless systems. The need for different types of wireless systems has been increased rapidly during the last few years. WLAN and cellular technique were developed accordingly to cater needs of different applications. Cellular technique is used for wide area, high mobility, but at slightly lower data rate and WLAN has higher data rate but small range. The success of these two concepts made it mandatory for the designers and researchers to provide multi-standard transceiver.

However, the design of multi-standard transceiver poses some challenges because it should be comparable with a single standard transceiver in size, cost and power consumption, while satisfying each standard’s requirements. These requirements call for the minimization of component number and large scale integration.

From the moment up to now, wireless communication experienced explosive growth and become the fastest growing field in the engineering world. New generation of wireless technologies brought new features and more complexity. Semiconductor industry has provided new technology for solid state circuit implementation. Fortunately, at the same time the cost reduction, performance of new technology has been improving. Hence a perfect combination between emerging wireless technology and the semiconductor industry is the reason for such progress in the field of wireless communication.

Necessity of Multistandard Receiver:

Nowadays, the requirements of multi-standard receiver that support many wireless standards are rapidly increased. New generation wireless communications needs the high integration of various systems. The main advantage of the multi-standard receiver is increase hardware flexibility and functionality, more immunity to interferers due to high image rejection, enhanced performance and condensed power consumption. In future there will be improvement in hardware reusability, reconfigurability and programmability. This will be first step towards software defined radio.

In this paper we present a comprehensive survey of multi-standard, multi-mode transceiver architecture and their performance. The section I, describes types of basic radio receiver architecture. In section II, we explain basic structure of RF transceiver integrated circuit for various standards. The section III shows single mode transceiver for complete transmission and reception of signal. In section IV a dual mode transceiver for 802.11a/b/g, WLAN, GPRS is explained. In section V the information about triple mode transceiver for 802.11a/b/g WLAN system are presented. The section VI describes quad band transceivers for GSM and GPRS applications. In section VII we present concluding remarks about the performance comparison of multi-standard receiver.

[I] Basic Radio Receiver Architecture:

1) Tuned Radio frequency Receiver: Figure 1 shows the block diagram of first ever radio receiver. In this the incoming signal from the antenna is passed through band pass filter to act as input to radio frequency amplifiers. The signal is amplified by RF amplifier. The amplified signal is detected by diode detector. Finally the base band signal is reconstructed by the comparator.

Fig.1: Tuned radio frequency amplifier

Ref: RF & Wireless Technology, ELSEVIER, www.newnespress.com

2) Superregenrative Receiver: This receiver has high sensitivity and minimum number of components. The high sensitivity is obtained by generating a negative resistance to cancel the losses and improve the quality factor. This is done by introducing positive feedback around the input stage figure 2 shows the block diagram.

If the oscillations have been established then the circuit reaches cutoff bias and oscillations stop until the conditions for the positive feedback are reinstated. Dynamic range of this receiver is limited.

Fig. 2: Super regenerative receiver

Ref: RF & Wireless Technology, ELSEVIER, www.newnespress.com

3) Superhetrodyne Receiver: This receiver is used for conventional radio communication. The signal is passing through the antenna and antenna is followed by the band pass filter that passes all signals within the range of receiver. The mixer and oscillator will generate a new signal. This signal is demodulated in the detector. The low pass filter is used for the noise reduction that follows the detector. The signal conditioning stage converts the base band signal to the designed signal form.

Fig. 3: Superhetrodyne receiver.

Ref: RF & Wireless Technology, ELSEVIER, www.newnespress.com

4) Direct Conversion Receiver: The Direct Conversion receiver is same as superhetrodyne receiver. In DCR a local oscillator and mixers for Zero IF is used. Low pass filter is used for the high sensitivity, high noise and adjacent channel interference rejection. Direct conversion receiver has very narrow bandwidth so crystal controlled local oscillator must be stable and accurate.

Fig. 4: Direct conversion receiver

Ref: RF & Wireless Technology, ELSEVIER, www.newnespress.com

6) Digital Receiver (software Radio Receiver):

Fig. 6: Software radio receiver

Ref: RF & Wireless Technology, ELSEVIER, www.newnespress.com

Digital receiver is also called as Software defined radio. The construction of digital receiver is same as superhetrodyne receive. The signal from antenna is amplified by low noise amplifier and then down converted by mixer and local oscillator to an intermediate frequency. Because of software flexibility, high performance and high efficiency is achieved.

Section II (Basic Block Diagram of Transmitter and Receiver)

Fig.7: Block Diagram of Transmitter and Receiver for various standards:

Ref: Adaptive multi-standard front ends, Springer

A transceiver consists of transmitter and receiver on a single module. The receive path start with an RF front-end. It has to control interferers and to increase the strength of received high-frequency analog signals and to down-convert them to a low IF. The IF strip has to given an additional filtering and amplification. At the end of the front-end, an Analog to Digital Converter changes the low-frequency analog signals into the digital signals. The all-purpose, Digital Signal Processing, block carry out all or some of the following operations: demodulation, equalization, de-interleaving, decoding and voice decompression.

Section III (Single Mode Transceiver)

A 2-GHz CMOS Image-Reject Receiver with LMS calibration:

Fig.8: Receiver architecture

Ref: IEEE journal of solid state circuits, vol. 38 No.2 Feb 2003

A LMS calibration technique has been introduced that largely improves the image-rejection of a Weaver receiver without negotiating the noise, linearity, or gain of the receiver. The Weaver architecture was selected because it suggests wideband image-rejection ability and low noise. An LMS calibration technique has been used to adjust the gain and phase mismatches only in the IF and baseband sections of the receiver, with minimum effect on overall receiver performance.

Performance:

The receiver has been tested with 2.5 V supply voltage. The measured input return loss in WCDMA band (2.11 to 2.17 GHz) is -11 dB. The receiver has 5.2 dB noise figure and voltage gain is 41 dB. The third order nonlinearity of the receiver is calculated. The blocking level is up to -33 dBm. These measurements show that the linearity of the receiver is limited by the second down conversion mixer. The sign-sign LMS calibration improves the image rejection ratio from 25 to 57 dB.

A low –Power Highly Digitized Receiver for 2.4 GHz Band.

This receiver explains the design and measurement outcome of low power highly digitized receiver for GFSK modulated input signals. They use LO IF architecture which gives linear receiver chain without limiters. A fifth order poly-phase loop filter is used in the complex ∑∆ ADC. The digital block executes the operation of filtering and demodulation. Channel filtering is shared with matched filtering and reduces noise resulting from the ∑∆ ADC. The high degree of digitization results into design flexibility with respect to varying standards and scalability. The only external components are antenna, filter and a crystal.

Fig.9: Block diagram of Receiver

Ref: IEEE transactions on Microwave theory and techniques Vol 53 No.2 Feb 2005.

Performance:

The measured total power consumption of various blocks of the receiver was 31.7 mW. The measured and simulated behavior of the demodulator is evaluated. The difference of Signal to Noise ratio is around 3 dB which can be found by extrapolating the measured line. The sensitivity level is -71 dBm. The dynamic range of analog to digital converter is 76 dB. The noise figure of radio frequency front end is 25 dB which is very high. The value of IIP3 is -10 dBm.

A Fully Integrated Zero-IF DECT Transceiver.

The single chip RF transceiver for DECT offers a complete transmission and reception radio interface between the antenna and the baseband digital bit stream. In this implementation maximum number of external component are reduced. The integrated phase locked loop synthesizer has a fast settling time and stays closed loop for the direct up conversion transmitter.

Zero IF technique is accepted in the receiver. An integrated low pass filter substitute the external SAW channel filter needed in the heterodyne receiver. The LNA is a simple cascade common emitter input stage, with a feedback resistor for input impedance matching. Variable gain amplifier which create signal levels fixed to the ADC input range. Since the accumulated offset of the previous blocks would saturate the VGA output, an offset compensation loop is implemented, which is active during the DECT guard band time. Direct up conversion topology is used for the transmitter section. Digital I and Q signals with a Gaussian filter shape are calculated from the transmitter input bit stream.

Fig.10: Transceiver Block Diagram

Ref: 2000 IEEE International Solid State Circuits conference 07803-5853-8 /00

Digital offset compensation and amplitude regulation removes LO leakage and mirror signal and lay down nominal output power. The 3.8 GHz VCO signal is distributed to the receiver and transmitter mixers and it is only locally divided to LO frequency.

Performance:

The DECT transceiver uses 35 mA in receiving section and 70 mA in transmitting section from 2.7 V to 3.6 V supply. The measured phase noise is -105 dBc/Hz at 1 MHz offset and 133 dBc/Hz at 10 MHz the current consumption of synthesizer is 10 mA. The noise figure is 2.2 dB. The sensitivity is obtained -96 dBm for 10-3 bit error rate.

Section IV (A Dual Mode Transceiver)

a) A dual Mode 802.11b/Bluetooth Radio in 0.35µm CMOS

Fig.11: Dual mode Transceiver architecture

Ref: ISSCC 2003 /SESSION 5 /WIRELESS-PAN TRANSCEIVER /PAPER 5.1

The IEEE802.11b standards offers short range data communication in LAN at data rates up to 11 Mb/s. This receiver targets a design of a low cost, low power and highly integrated 2.4 GHz 802.11b radio which also supports the Bluetooth standard.

The transmitter applies direct conversion architecture to get low power consumption and high level integration. A power amplifier consisting of a pre-amplifier and driver stage which increases this signal and distribute a nominal power. To keep away from PA pulling issues, a clock generator creates a clock frequency that matches with the RF signal at the transmitter output.

The Bluetooth receiver uses a low IF architecture with an intermediate frequency of 2 MHz to incorporated the channel select filter. DC offset is cancelled by a programmable offset cancellation loop in the IF section, restricted by the base band chip.

Performance:

The performance of transceiver was measured and the reported sensitivity is -88 dBm at 11 Mb/s and -93 dBm at 2 Mb/s. The noise figure is 5.5 dB. The maximum input signal for the transceiver can be as large as +10 dBm. The minimum IIP3 of the receiver is -8 dBm. In this transceiver measured adjacent channel rejection ratio is 35 dBc. The average modulation accuracy is around 20%.

b) A CMOS WLAN/GPRS Dual-mode RF front-end Receiver

A dual-mode, tri-band RF receiver for GSM 900, DCS 1800 and IEEE 802.11b/g is designed with highly developed architecture and frequency plan. Only single VCO and frequency synthesizer is used for both GSM/GPRS cellular and 802.11b/g WLAN.

Fig.12: Block diagram of RF front end receiver

Ref: 2004 IEEE Radio frequency Integrated Circuits Symposium.

The noise performance of this receiver is calculated by hot cold method. Image rejection ratio is calculated by the amplitude and phase accuracy of the quadrature local oscillator and circuit by variance between I and Q path. The frequency plan also provides an offset LO scheme to discourage unwanted communications between the RF and LO signals. It is reported that by adding a programmable bandwidth amplifier in this dual band receiver this design will be useful for future standards.

Performance:

This design supports three standards; the noise performance is measured by hot-cold method. A noise figure is 3 dB for GSM 900, 5.9 dB for DCS 1800 and 5.7 dB for 802.11b/g band has been achieved.

c) A Single-chip, 5.15 GHz-5.35 GHz, 2.4 GHz-2.5 GHz, 0.18µm CMOS RF Transceiver for 802.11a/b/g Wireless LAN

This work describe a single chip, 0.18µm CMOS direct conversion, dual band radio transceiver combining the existing IEEE 802.11a/b and promising IEEE 802.11g standard necessities.

In this design both transmitter and receiver uses direct conversion method. The architecture consists of independent paths for transmitter and receiver signals. An LNA for receive path is independently designed along with quadrature demodulation for 2.4 GHz to 5.4 GHz. The output of the receiver is digitized by a dual 10 bit, 40 MHz ADC.

The transmit path also contains dual I/Q fourth order Chebyschev filter and separate programmable gain modulation and drive amplifier.

Fig.13: Transceiver block diagram

Ref: Athena Semiconductors’

Performance:

It reported that the transceiver is implemented on 0.18 μm 1P6M CMOS technology. After implementation measurements were conducted to test the performance. The designed transceiver achieves a noise figure of 5.2 dB for the receiver path with a sensitivity of -76 dBm at 5 GHz band. In case of 802.11a at 54 Mb/s the noise figure obtained is 3.5 dB with sensitivity of -92 dBm.

Section V (Triple Mode Transceiver)

a) A Low-Power Dual-band Triple-Mode WLAN CMOS Transceiver

The designed transceiver supports dual band WLAN system with frequency range of 2.4 GHz to 2.5 GHz and 4.9 to 5.95 GHz, and the channel bandwidth of 5 to 24 MHz

This transceiver is designed with a direct conversion dual-band triple-mode wireless LAN. The transceiver has a synchronized dual-band low noise amplifier for low power consumption with a low noise figure and a single tunable low pass filter biased for multi mode operation with low power. A DC offset compensation circuit with an adaptive activating feedback loop to get a rapid response time with low power consumption is designed and a ∑∆-based low phase noise fractional N synthesizer with a switched resonator voltage controlled oscillator is added to track the entire frequency range.

Fig.14: Transceiver Block diagram

Ref: IEEE journal of solid state circuits Vol. 41, No 11, Nov 2006.

Performance:

The transceiver is tested for WLAN working in the band of 2.4 GHz and 5.2 GHz. The maximum gain is 75dB for both frequencies. The noise figure of 3.5 dB and 4.2 dB obtained for 2.4 GHz and 5.2 GHz respectively. In receiver maximum current consumption is 78 mA. The noise figure deviation is very small. The integrated rms phase error of 1.70 and 1.870 is achieved for 2.4 GHz and 5.2GHz respectively. The sensitivity of -93 dBm and -94 dBm was observed for receiving section at 2.4 GHz and 5.2 GHz respectively.

Section VI (quad band transceivers)

A Single-chip RF Transceiver for Quad-band GSM/GPRS Application

This design presents a single chip quad band transceiver with fully integrated VCO’s. It also integrates all RF and analog functional blocks including Low IF receiver, frequency synthesizer, and phase lock loop, three VCO’s and low drop out voltage regulator.

Fig.15: The transceiver functional block diagram.

Ref.: 2004 IEEE Radio Frequency Integrated circuits Symposium.

The receiver is based on analog low IF architecture which includes four fully differential cascode LNA for quad band operations. Channel filters and PGA is also integrated. The I/Q demodulator is implemented based on analog complex mixer

Performance:

The design is implemented on 0.35μm BiCMOS process with cut off frequency of 29 GHz. The test result demonstrates that noise figure is below 5.50. The receiver sensitivity achieves -78 dBm. It was also demonstrated that dynamic range of the receiver is 110 dB.

b) A Single-chip Quad band Direct Conversion GSM/GPRS RF Transceiver.

This is one chip direct conversion transceiver. A monolithic IC integrates all the active RF functions of a quad GSM receiver except for the PA. A direct conversion receiver and an up conversion loop transmitter use a fractional-N PLL and fully integrated transmit and UHF VCOs.

In transmitter, no saw filter or external VCOs is needed and digitally calibrated VCO tuning permits quad band operation. Complete LO integration means the only RF signals are receiver inputs and transmitter outputs. This reduces RF bond wire coupling.

Performance:

Noise figure of receiver is 3.1 dB for GSM, 3.6 dB for DCS, 4.1 dB for PCS. Minimum achievable sensitivity is -109 dBm in GSM, -107 in DCS/PCS. UHF VCO and Fractional synthesizer gives a wide tuning range is 1200MHz to 1700MHz. UHF lock time is 175µsec.

Fig.16: Block diagram

Ref: ISSCC 2002 / SESSION 14 / CELLULAR RF WIRELESS /14.2

c) The First Fully Integrated Quad-band GSM / GPRS Receiver in a 90 nm Digital CMOS process.

The receiver is a single chip GSM/GPRS transceiver that incorporates full integration of quad band receiver, transmitter, memory and power management unit. The architecture uses Nyquist rate direct RF sampling in the receiver and an all digital phase locked loop for generating the local oscillator.

A feedback loop is provided to the mixer output and can be used to cancel DC offset as well to check the linearity of the receiver chain. This test chip does not integrated the digital base band processor, however an ARM7 subsystem is integrated to study noise coupling impacts of deep submicron integration.

Fig.17: First Single chip GSM Transceiver.

Ref: IEEE Journal of solid state circuits, Vol. 41 No. 48 Aug. 2006.

Performance:

The sensitivity of the receiver is -110 dBm. The maximum current consumption reported is 60 mA with supply voltage 1.4 V. Receiver gives an IIP2 of 46 dBm and IIP3 of -25 dBm at the noise figure of 2 dB. IIP3 is improved by 5 dBm in second feedback loop. Using the I/Q mismatch circuit image rejection ratio is improved from 40 dB to 55 dB.

d) A Single Chip Direct Conversion CMOS Transceiver for Quad-band.

A multi-standard, multi-band RF transceiver that meets various mobile standard requirements is designed for quad band operation. Direct conversion type receiver provides the highest integration for a multi-standard multi-band transceiver. However direct conversion produces DC offset that will damage narrowband GSM signal. In Up conversion the signal is converted from analog baseband to RF. A local oscillator is designed to generate a carrier frequency. Direct modulation is used in the architecture for GSM, EDGE and WLAN. Delta sigma frequency synthesizer is used for further improvements.

Fig.18: Block diagram of Transceiver IC

Ref: 2004 IEEE Radio Frequency Integrated Circuit Symposium.

Performance:

Voltage controlled oscillator frequency is 3.4 GHz to 3.9 GHz. The gain of transceiver achieved is 95 dB. The designed low noise amplifier consumes 18 mW. The value of IIP2 reported is 45 dBm. Phase error achieved is less than 10.

Section VII (Concluding remarks)

In this paper, we present the comparative performance evolution of reported multi-standard receiver. The paper begins with introduction and basics of radio receiver and describes various transceiver architectures reported. The present state of wireless receiver uses a direct conversion low IF or zero IF architecture. The survey begins with single mode transceiver to the latest quad band SoC design. The operation of the transceiver in multi-band is easy for the design than multi-standard. The issue of the RF isolation is critical in case of multi-standard. In the advent of software defined radio and zero IF architecture the multi-band, multi-standard design of transceiver will be simple in operation and more useful to support reconfigurability of the receiver.