Efficient Low Power Cmos Pll Computer Science Essay

Published Date: 02 Nov 2017

NITHA RAJ K.R, Mrs. SUNITHA.V

II M.E. Embedded System Technologies, Asst.professor

Sun College of Engineering and Technology

[email protected]

Abstract-Phase locked loops find wide application in several applications mostly in advance communication and instrumentation systems. In this paper the concept of in-loop filters in phase-locked loop (PLL) systems is discussed. These filters can be either derived analytically or using conventional window function. Here we introduce methods related to window function into PLL systems. This method enables smoother estimation of the signal parameters such as phase angle, frequency, and amplitude in the presence of noise and harmonics. The in-loop filters can be adjusted to completely remove specific harmonics. The method is developed for enhanced PLL system. Different PLL analysis is also carried out. CMOS processes have been traditionally optimized for digital applications, which have given an even higher importance to the design phase. Furthermore, the increased need for mobility within modern communications requires the devices to minimize their power consumption.

Key words—Discrete Fourier transform (DFT), enhanced phase locked loop (PLL) (EPLL), in-loop filters, PLL, windowing, CMOS.

I. INTRODUCTION

The Phase Locked Loop (PLL) is one of the most ubiquitous electronic components found in almost every electronic device from televisions to mobile phones, with a wide range of applications including frequency synthesis, clock data recovery, AM and FM demodulation, motor speed control, FSK decoders. The pervasiveness and popularity of the PLL is due to the robust nature and spectral purity of the PLL output signal, which are impossible to realize without the use of the PLL loop.A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. This circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop. A phase-locked loop can track an input frequency, or it

can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.

A PLL is often envisaged as a nonwindow method in the sense that it does not use a specific length of measured data but it rather uses only the current instant of a signal. This is unlike the discrete Fourier transform (DFT) or fast Fourier transform (FFT) which use a number of signal samples to perform computations at each instant. The window function in DFT is rectangular, but it has been conventionally extended to various different forms such as the Hann, Hamming, Blackman, and Kaiser windows among many others. A distinguished feature of the rectangular window is in its ability to completely remove the errors caused by different harmonics.

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Fig: 1Block diagram of PLL

This paper investigates the concept of applying window functions to PLL systems. It is first shown that the window functions correspond to in-loop filters. The filters are studied from a perspective that generalizes the PLL instantaneous cost function to a window-based cost function. An analytical method to design the parameters of the window-based PLL is presented. It is rigorously shown that the in-loop filters (or windows) play a crucial role in the PLL performance and stability, and they must be designed carefully to avoid performance degradation. Two particular types of rectangular window and low-pass filter are analyzed. It is observed that those windows can improve the PLL performance against high-frequency harmonics. Furthermore, the rectangular window can be adjusted to block specific frequency components or harmonics similar to what is performed in DFT. The study presented in this paper is performed on the single phase enhanced PLL (EPLL).The generality of the proposed method and analysis makes it easily applicable to other types of PLL.

II. RELATED WORKS

The conventional concept of windowing is widely used in DFT-type algorithms, but it is never systematically introduced for PLL systems. This paper has extended the very structure of the PLL systems to accommodate this concept. The concept is first developed for a single-phase EPLL from a cost function minimization perspective. It is then extended to a conventional three-phase SRF-PLL. The same method is practically applicable to other types of PLLs. This paper has also introduced a method for designing the PLL gains in the presence of window functions. The rectangular window is particularly treated where it can block specific harmonics.

The windowing can thus improve the steady-state responses in terms of smoothness and accuracy. [1] describes the use of PLL in synchronization of power quality instruments. In this paper, the problem of instrument synchronization has been analyzed, showing how the techniques that are proposed in literature can be adversely affected by the application of a disturbing influence on the electrical input signal. Then, two new synchronization strategies have been introduced. The former is based on signal spectral analysis techniques that are performed by means of the CZT analysis. The latter is a PLL software that is based on a time-domain coordinate transformation and an innovative phase-detection technique.

The application of PLL for fast frequency and phase acquisition is described in [2]. Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The lock time of the PLL mainly depends upon the type of PFD architecture used and the parameters of the charge pump and loop filter. So by properly choosing the PFD architecture and adjusting the charge pump current and the loop filter component values we can achieve a better lock time.

PLL has different varieties. Digital PLL is described in[3]. Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs. There are several key points required for high performance D-PLL circuits design such as power efficiency, loop bandwidth flexibility and accurate frequency translation. This paper describes a novel D-PLL architecture and presents an analysis of the digital loop filter.

Power quality instrumentation requires accurate fundamental frequency estimation and signal synchronization, even in the presence of both stationary and transient disturbances. In this paper[4], the authors present a synchronization technique for power quality instruments based on a single-phase software phase-locked loop (PLL), which is able to perform the synchronization, even in the presence of such disturbances. Moreover, PLL is able to detect the occurrence of a transient disturbance.[5]The increasing sensitivity of more sophisticated devices require special attention to harmonic pollution. In this paper, we have tried to elaborate more effective methods for harmonic analysis of signals (by referring to the signal power supply) through the use of PLLs; in particular we focused on the task of making the system more efficient.

The architectures of TDC- and accumulator-based ADPLLs is described in [6]. Then, briefly describing the block and timing diagrams of Gated-Ring-Oscillator-based and Local Oscillator-based TDCs. Paper presents the governing equations of both TDCs and we calculate the resolution of the "first order noise shaping TDC plus moving average filter" system. Itis shown briefly the effect of the phase error on the output of the "LO TDC plus moving average filter" system and proposed an extended LO TDC that can measure the phase error. Derived equations to predict the resolution of the extended LO TDC and confirmed the predictions with Matlab simulations. Finally, we compare in simulation the power spectral densities of the phase errors of a Gated-Ring-Oscillator-based ADPLL and of an accumulator based ADPLL with the extended LO TDC.

Type-II charge-pump (CP) phase-locked loop (PLLs)are used extensively in electronic systems for frequency synthesis which is described in[7].Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional- PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which toper form the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage.

III. PROBLEM DEFINITION

A low pass filter generally has two distinct functions. The primary function is to determine loop dynamics, also called stability. This is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to the VCO control input. This frequency modulates the VCO and produces FM sidebands commonly called reference spurious. The errors can be reduced by performing a suitable windowing operation and/or using correction interpolation algorithms. However, these methods limit but do not remove errors and entail an extra computational cost: moreover, these procedures are accurate only when no harmonic and interharmonic signal pollution occurs. Frequency synthesis is one of the applications of PLL using DSS technology.

Fig:2 Block diagram of Frequency Synthesizer

In the EPLL, fig:2 the primary objectives are to estimate the frequency, amplitude, and phase angle of the fundamental component of a given signal u(t) and also to provide a robust signal for synchronization. Enhanced PLL enhances conventional PLL by adding a new branch that estimates the amplitude and by adding an outer loop that removes the double frequency ripple from the whole system. The in-loop filters (fig:3) or window functions have very direct and strong impact on the system responses and can even quickly cause instability if they are not properly designed.

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Fig: 3EPLL structure: A, ω, and φ are the estimated amplitude, frequency and phase angle and S is the synchronizing signal.

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Fig:4 EPLL structure with windowing (or in-loop filtering).

IV. PROBLEM EVALUATION

In this paper enhanced phase locked loop is analyzed. Mathematical analysis is done and transfer function is derived .This transfer function is analyzed to find out the stability of the system. First analysis is about the in loop filters and later the analysis covers all the components of phase locked loop. Simulink/Matlab is used to analyze the whole module. In the EPLL, the primary objectives are to estimate the frequency, amplitude, and phase angle of the fundamental component of a given signal u(t) and also to provide a robust signal for synchronization. To achieve these tasks, assume that y(t) is an estimate of the fundamental component provided by the EPLL. This signal can be written as y(t) = Asinφ, where φ =∫0tω dτ+ δ and δ is the initial phase angle of the input signal at time zero. The EPLL equations are derived based on minimizing the cost function J =1/2e2=1/2(u − y)2. The derived equations using the gradient descent method can be expressed as

.

A =μ1 e sin φ

.

Δω =μ2 e cos φ

.

φ=ω0 +Δω + μ3 e cos φ

whereω0is the system nominal frequency and Δωis the deviation from this frequency. A block diagram of the EPLL based on equation set (2) is shown in Fig. 1. The triplet (A, ω, φ)denotes the estimated amplitude, frequency, and phase angle. The signal S = sinφis the synchronized (or synchronizing) signal. It is observed from fig:2 that the EPLL enhances the conventional PLL by adding a new branch that estimates the amplitude and by adding an outer loop that removes the double frequency ripple from the whole system.

Root locus analysis is a graphical method for examining how the roots of a system change with variation of a certain system parameter, commonly a gain within a feedback system. By selecting a point along the root locus that coincides with a desired damping ratio and natural frequency a gain, K, can be calculated and implemented in the controller. For stability, all poles must lie in the left half of the s-plane. The relationship of the system poles and zeroes then determine the degree of stability.

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Fig:5 Pole locations

The root locus plots the poles of the closed loop transfer function as a function of a gain parameter. In addition to determining the stability of the system, the root locus can be used to design the damping ratio and natural frequency of a feedback system. Lines of constant damping ratio can be drawn radially from the origin and lines of constant natural frequency can be drawn as arcs whose center points coincide with the origin. The definition of the damping ratio and natural frequency presumes that the overall feedback system is well approximated by a second order system; i.e. the system has a dominant pair of poles. The graph or plot illustrates how the closed loop poles (roots of the characteristic equation) vary with loop gain. For stability, all poles must lie in the left half of the s-plane. The relationship of the system poles and zeroes then determine the degree of stability.

Fig. 6 Root locus of the dominant poles of the amplitude estimation loopwhen a rectangular window of lengths Tw = 5, 10, and 15 ms is used in this loop.

V. FUTURE ENHANCEMENT

In this paper filter analysis is done for a single-phase enhanced PLL system and is then extended to three-phase PLLs including the well-known synchronous-reference-frame PLL. This can also be done for different types of other filters like analog phase-locked loop (APLL) also referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL), and software phase-locked loop (SPLL).Transfer function for all these filters are analyzed and root locus is plotted to identify the stability of the filters in different types of PLLs. The fig 3 shows the analysis using root locus. Windowing technique is also included to enhance the performance of the filters. The analysis can be further considered for all components in PLL.One of the application of PLL is frequency synthesis. Frequency synthesizers are widely used in modern communication systems. There are many frequency synthesis technologies such as direct analogy synthesis (DS), the DDS, the PLL and the mixture of the former technologies, etc. The DS has advantages of fast hopping time and high output frequency but it also has the disadvantages of requiring large amount of hardware and high intermodulation distortion. The DDS can generate small frequency step sizes and tune fast but has shortcomings of high spur levels and low output frequency. The PLL has to tradeoff between frequency step size and phase noise. In order to achieve better performances, the research on the hybrid frequency synthesis technology such as the DS-PLL, the DDS-PLL, the DS-DDS and the DS-PLL-DDS, is very popular and challenging.

System modeling is an important part of any design process; it assists in system analysis and the determination of the expected system performance either analytically or through simulation, by predicting the logical behavior of the system. MATLAB/SIMULINK is used for simulation. MATLAB is a high-level language and interactive environment for numerical computation, visualization, and programming. MATLAB can be used to analyze data, develop algorithms, and create models and applications.

Tanner tool is used for system level design. Today's designers of analog/mixed signal ICs, ASICs and MEMS face many challenges such as shorter time-to-market cycles, increasing cost constraints, and a lack of resources. That is why many designers rely on Tanner Tools to help them meet these challenges.

VI. CONCLUSION

The conventional concept of windowing is widely used in DFT-type algorithms, but it is never systematically introduced for PLL systems. This paper has extended the very structure of the PLL systems to accommodate this concept. The concept is first developed for a single-phase EPLL from a cost function minimization perspective. The same method is practically applicable to other types of PLLs. This paper has also introduced a method for designing the PLL gains in the presence of window functions. The rectangular window is particularly treated where it can block specific harmonics. The overall conclusion is that windowing can significantly improve the steady-state responses in terms of smoothness and accuracy. The tradeoff is, however, made with the speed of responses. A moderate selection of window length can offer some good improvement against noise and high-frequency harmonics (even imbalance) without much slowing down the responses. It is worth mentioning that the window functions are implemented using in-loop windows (or filters). This is fundamentally different from using pre- or post-filter before processing or after an estimation process.