Data Converters In Software Defined Radio Computer Science Essay

Published Date: 02 Nov 2017

Author Name

ECE Department

NIT Warangal

Email:

Abstract—Software defined radios have an edge over conventional

radios. For effective implementation of SDR technology

choosing suitable data converters is necessary. This paper describes

the requirement of data converters in SDR, their key

specifications that impact the SDR performance and the data

converters offered by leading vendors which are suitable for SDR

design.

I. INTRODUCTION

The entire signal processing in Software defined radios is

performed in digital domain. With the emergence of powerful

DSP processors development in SDR has accelerated. These

Software defined radios provide high degree of flexibility and

high performance. But the input from RF antennas is an

analog signal which needs to be converted to digital signal

before applying digital signal processing techniques. So data

converters act like catalysts in successful implementation of

SDR technology.

Many wireless technologies like GSM,CDMA, WiMax,

WiFi, 3G and 4G have evolved in recent years. End users

expect to have all these functionalities in one single device.

SDR provides the reconfigurable architecture which implements

many functions that were traditionally implemented

using analog circuitry.

Wireless standard Operating Frequency

GSM 850MHz,900MHz,1800MHz

CDMA 824-844MHz,869-

889MHz

Bluetooth 2.4GHz

Wimax 2500MHz,3500MHz and

all the way to 5GHz

TABLE I: Operating Frequencies of different wireless standards

Table I describes the operating frequencies of various wireless

standards. From the table it is clear that ADCs in SDR

that receive RF signal directly need to have a bandwidth up

to 5GHz and should operate at sampling frequency of twice

the signal bandwidth. As the receiver in SDR is a wideband

receiver, the ADC in the receiver must have high resolution

in order to detect weak signal in presence of other channels.

Leading vendors are offering ADCs operating over 100MSPS

at 12+ resolution with input analog bandwidth up to 1GHz.

II. KEY SPECIFICATIONS OF ADC

Many factors determine the performance of ADCs but

there are few specifications of interest that impact SDR

performance. The contribution of these key specifications is

discussed below. [1]

A. Analog input bandwidth

Analog input bandwidth is the most important specification

in high sampling rate wide band applications. ADC’s input

bandwidth depends on the shape of the input signal. Most

of the common input signals are bandlimted while wider

bandwidths are required for signals such as transient events.

As SDR implements many functions of different operating

frequencies wider input bandwidth is required. Wider input

bandwidth provides better slew rate performance and accurate

sampling of input signal. [2]

Wider bandwidth allows more noise into ADC.On sampling

this signal the noise is widely spread and by filtering the excess

noise is removed. But bandwidth parameter of an ADC needs

some more improvement until then analog mixing to translate

RF signal to IF band is used before ADC process. Today there

are many commercially available high speed, high resolution

ADCs which eliminate 2nd IF stage in SDR technology. ADCs

with input bandwidth of 1GHz are offered by leading vendors

and production of even high speed ADCs improves every year.

B. Signal to noise ratio

When the received input power from RF antenna is low the

SNR of ADC becomes an important parameter of the receiver.

The noise in an ADC is caused due to quantization noise,

internal noise and aperture jitter. This noise is uniformly

spread throughout the frequency band. The digital filter selects

frequency band of interest where the signal energy is present

and passes only portion of ADC noise thus improving the SNR

of ADC. By increasing the number of encoded bits the effect

of quantization noise can be minimized. But oversampling

technique introduces improvement a in SNR of ADC. The

SNR with oversampling improvement effect is given by [7]

SNR = 6.02n + 1.76 + 10 log fS/2

BWSIG

where n is number of bits, fS is sampling frequency and

BWSIG is the bandwidth of the signal. So from the above

equation it is clear that instead of increasing n(number of bits)

by increasing the sampling rate better SNR can be achieved.

This SNR improvement is called Processing gain and is given

by

PG = −10 logBWSIG

fS/2

ADC Maximum

Conversion

Rate

Resolution Bandwidth SNR & SINAD SFDR Jitter

AD9862(MxFE) 64 MSPS 12 Bit 140 MHz 64.2dBc & 64.14dBc 81.0dBc 1.2ps rms

AD6645 105MSPS 14 Bit 270MHz 75dBc & 74.5dBc 98 dBFS(two-tone) 0.1ps rms

AD9254 150MSPS 14 Bit 650MHz 71.8dBc & 71.0dBc -84dBc 0.1ps rms

ADS62P45 125MSPS 14 Bit 450MHz 73.6dBFS & 73.2dBFS 86dBc 150fs rms

ADC14DS105 105MSPS 14 Bit 1GHz 72.5dBFS & 72.3dBFS 85dBFS 0.1 ps rms

ADC12DS105 105MSPS 12 Bit 1GHz 70dBFS & 69.9dBFS 85dbFS 0.1ps rms

LTC2274 105MSPS 16 Bit 700MHz 75.1dBFS & 74.2dBFS 94dBc 80fs rms

ADS5562 80MSPS 16 Bit 300MHz 81.4dBFS & 80.2dBFS 83dBc 90fs rms

ADS5500 125MSPS 14 Bit 750MHz 72.3dBFS & 71.6dBFS 83dBc 300fs

LTC2208 130MSPS 16 Bit 700MHz 75.1dBFS & 75dBFS 83dBc 70fs rms

TABLE II: ADC and their specifications

0 0.5 1 1.5 2 2.5 3

x 108

−5

0

5

10

15

20

25

Bandwidth of the signal[Hz]

Processing gain(dB)

Fig. 1: Processing gain vs Signal Bandwidth at fs =

500MSPS

and figure 1 gives the relation between processing gain and

signal bandwidth. [8]

It should be checked that in imlementing oversampling

technique ADC should not reach its sampling rate limit.

Sigma-Delta ADC provides noise shaping and improves the

SNR of an ADC. Time-interleaved ADC systems can also be

used to achieve oversampling.

C. Clock Jitter

Clock jitter and aperture uncertainty represent the same problem.

Jitter also affects the SNR of the ADC. As frequency of

the signal increases the effect of aperture jitter also increases.

This is because the high frequency signals slew more in amplitude

during the period of uncertainty. The relation between

SNR and jitter is given by

SNR = −20 log10 (2fintjtr)

where fin represents the analog input frequency, and tj tr the

RMS value of the systems jitter. This implies SNR of the

system is affected by analog input frequency.

D. Spurious Free Dynamic Range

Spurious Free Dynamic Range is another key specification

of ADC.Figure 2 explains it clearly.It characterizes the linearity

of an ADC. It is the ratio of between the amplitude of

the analog input signals fundamental frequency and highestamplitude

spurious signal. SFDR becomes critical in situations

where the incident power at the receiver’s antenna is of

substantial power levels. This can happen when the wanted

signal is strong which is a desirable situation, or when an

in-band interferer is strong which is an undesirable situation.

When the interferer is strong it limits the ADC performance.

Since the total signal, i.e sum of wanted and interferer, already

approaches the full scale range of analog input signal. So the

linearity of ADC decides whether the wanted signal can be

effectively demodulated or not. The input signal should not

saturate.

In frequency domain,spurious signals appear as spikes at

different discrete frequencies. SFDR depends on the sampling

rate, analog input frequency, and analog input amplitude. By

reducing the input amplitude of the signal below the full scale

value the SFDR can be optimized.

III. KEY SPECIFICATIONS OF DAC

The key specifications of DAC are Noise power spectral

density (NSD), Adjacent-channel leakage ratio (ACLR) or

adjacent-channel power ratio (ACPR). DAC must be able to

synthesis higher frequencies. Inband and quadrature signals

are added and then fed to DAC. So there is high bandwidth

requirements of DAC for better performance of transmitter.

Adjacent Channel Leakage Ratio is defined as the ratio of

the power in the desired carrier band to the power in an

adjacent carrier band. The specification covers the first two

adjacent bands, and is measured on both sides of the desired

carrier. For perfect transmission the spurious products need to

be about -75dBFS.

Noise is the major concern of DAC. SDR application is

wideband in nature. As the signal from DAC is applied

to power amplifier, noise from DAC also passes through

the power amplifier. This excess noise when passed through

antenna gets converted into RF noise. So output noise density

Manufacturer DAC Resolution Update rate

Maxim MAX5879 14-Bit 2.3GSPS

Analog Devices AD9778 14 Bit 1GSPS

Analog Devices AD9744 14 Bit 210MSPS

Texas Instruments DAC3482 16 Bit 1.2GSPS

Texas Instruments DAC 5672 14 Bit 275MSPS

Analog Devices AD9957 14 Bit 1GSPS

Analog Devices AD9755 14 Bit 300MSPS

Analog Devices AD9739 14 Bit 2.5GSPS

Intersil ISL5961 14 Bit 210MSPS

Intersil ISL5929 14 Bit 210MSPS

TABLE III: DACs and their specifications

Fig. 2: Spurious free dynamic range[ [3]]

from DAC must be as minimal as possible. DACs provided

by different vendors have better output density.

Spurious Free Dynamic Range of a DAC is the usable

dynamic range of a DAC before spurious noise interferes

with the fundamental signal. SFDR is the measure of the

difference in amplitude between the fundamental and the

largest harmonically or non-harmonically related spur from

DC to the full Nyquist bandwidth.SFDR over full Nyquist

bandwidth and band of interest of application has to specified.

Selecting a low glitch, linear converter helps to significantly

reduce spurs.

IV. OTHER FEATURES

Integration plays a very important role in enhancement

of performance. Converters with digital filters, interpolators,

decimators, NCOs also help in transceiver action. In recent

years the converters with above digital functions are available

in the market. An NCO in a DAC with interpolation translates

the baseband signal to anywhere in the Nyquist band of

interpolated sample rate. Similarly in ADC an on-chip NCO

with decimator converts the IF signal to baseband signal.

Another Benefit of on-chip decimators in ADCs and interpolators

in DACs is it lowers the external interface speed which

reduces the switching speed requirements by just allowing

to use slower logic families which inturn lowers the overall

noise and spurious generated in data converters. So with

the evolution of high performance conveters with levels of

integration improves the performance of SDR systems.

V. DATA CONVERTERS IN SDR

A. Analog to Digital converters

For meeting todays radio requirements 12 or 14 bit ADCs

are sufficient and sampling rate > 100MSPS is preferred.

Table II presents the ADCs used in various SDR platforms

and their key specifications.[ [3] c [6] ]

National Semiconductor’s [9] ADC12Dxx00RF ADCs provide

sampling rate from 1.0 to 3.6GSPS. They are 12-bit

ADCs with five sampling rates viz., 1.0, 1.6, 2.0, 3.2, and

3.6 Gsamples/s. They are dual channel ADCs with completely

independent signal chains. It can be operated in interleave

mode to implement alternate sample of each channel. The best

feature of these ADCs is that they eliminate the requirement of

multiple IF stages. By limiting the hardware implementation

of these IF stages bill of material cost,board size,weight

and power consumption reduces drastically. Elimination of

Local oscillators reduces the effect of interference.The 3.6-

Gsample/s device boasts third-order intermodulation distortion

(IMD3) of -71 dBc at 2.7 GHz with an amazing noise floor

of -152.2 dBm/Hz.

To meet the SDR need for superior performance to recover

data with very high sensitivity from multiple channel,

wideband input RF applications and frequency flexibility

Texas Instruments has introduced 1GSPS ADCs,

ADC12D1800/1600/1000, which are of 12-bit resolution.

Texas Instruments [10] also manufactured dual channel 12-

bit and 14-bit ADS61xx series. It provides a sampling rate of

250MSPS.Its high dynamic performance and low power consumption

makes it suitable for multicarrier, wide bandwidth

communications applications like SDR. Linear Technology’s

[11] 16-bit LTC2208 provides sampling rate of 130MSPS.It

digitizes wide range of signals with input bandwidth up to

700MHz.PGA can be used to optimize the input signal.It has

78dBFS Noise Floor and 100dB spurious free dynamic range

(SFDR).

B. Digital to Analog Converters

A 14+ bit resolution DAC is preferred to meet the radio

requirements. Table III presents some of DACs suitable for

SDR design. [5]

Maxim’s MAX5879 RF DAC [12] works with FPGA-based

direct digital synthesizer and shifts the analog implementation

Fig. 3: Courtesy - Texas Instruments

into digital domain. This eliminates the use of analog local

oscillators and in turn the in phase and quadrature phase errors.

This simplifies the RF design and improves the transmitter performance.

A single MAX5879 RF DAC serves many wireless

standards without giving up the dynamic performance.

Texas Instruments DAC5688 is dual-channel, 16-bit, 800-

MSPS, digital-to-analog converter (DAC) with dual CMOS

digital data bus, integrated 2x-8x interpolation filters, a fine

frequency mixer with 32-bit complex numerically controlled

oscillator (NCO), onboard clock multiplier, IQ compensation,

and internal voltage reference. It can be operated in different

modes. It allows both complex and real outputs.

Input data of DAC5688 can be interpolated by onboard digital

interpolator. An additional 32-bit NCO in complex mode

provides frequency up conversion and the dual DAC output

form the Hilbert transform pair. A digital inverse sinc filter

is also present. The digital Quadrature Modulator Correction

(QMC) feature allows IQ compensation of phase, gain, and

offset to maximize sideband rejection and minimize LO feed

through of an external quadrature modulator performing the

final single sideband RF up conversion.

The DAC5688 provides many different modes of operation.

Single-sideband mode provides an alternative interface to

the analog quadrature modulators. Channel carrier selection

is performed at baseband by mixing in the ASIC/DUC.

Baseband I and Q from the ASIC/DUC are input to the

DAC5688, which in turn performs a complex mix resulting

in Hilbert transform pairs at the outputs of the DAC5688’s

two DACs. An external RF quadrature modulator then performs

the final single-sideband up-conversion. The DAC5688’s

complex mixing frequencies are flexibly chosen with the 32-

bit programmable NCO. In quadrature modulation mode, onchip

mixing provides baseband-to-IF upconversion. Mixing

frequencies are flexibly chosen with a 32-bit programmable

NCO. Channel carrier selection is performed at baseband by

complex mixing in the ASIC/DUC. Baseband I and Q from

the ASIC/FPGA are input to the DAC5688, which interpolates

the low data-rate signal to higher data rates. The DAC output

from the DAC5688 is the final IF single-sideband spectrum

presented to RF. [4]

Fig. 4: FFT output of 14 bit ADC. [Data generated from

ADIsimADC]

0 1 2 3 4 5 6

x 107

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Single−Sided FFT of input signal

Frequency (Hz)

dBFS

Fig. 5: FFT output of 14 bit ADC. [Matlab result]

VI. SIMULATION AND RESULTS

In this section the performance charachteristics of 14-bit

ADC with 250MSPS sampling rate is presented.This simulations

are performed in online tool ADIsimADC. Input signal

frequency is taken as 2.23MHz.The characteristics are shown

in figure 4

The simulation in matlab by considering only quantisation

noise for 14-bit ADC of 250MSPS sampling rate is as shown

in the figure 5

VII. CONCLUSION

The selection of suitable data converter is the key aspect in

the design of software defined radio. Because of advancement

in the field of high speed data converters many wide band

ADCs are available in todays market. With the familiarity of

latest offerings from different vendors and based on application

one can choose correct data converter for accomplishing

the design of SDR.