Compiler Directed Energy Reduction Of Embedded System

Published Date: 02 Nov 2017

Abstract

Power consumption is now a major constraint in embedded Systems design. As the speed of embedded processors becomes faster and more peripherals are integrated into a single chip, the multimedia applications that run on these devices become more computationally intensive. However, technological advance of the batteries which power the embedded systems lags significantly behind, and as a result, power consumption is one of the most important performance metrics for portable embedded systems. The approach is based on the ability to sample power consumption and to correlate each sample with the program's instruction sequence and, hence, with the source code. One difficulty is achieving high sampling precision. Ideally, power consumption should be sampled at the system clock's frequency, but power system capacitances reduce the reliability of such measurements. This paper presents a detailed study on necessary software compiler support for voltage islands. Specifically, it focuses on an embedded multiprocessor architecture that supports both voltage islands and control domains within these islands. It determines how an optimizing compiler can automatically map an embedded application onto this architecture. The experiments shown that the power consumption reduced to ….. by exploiting both data and task parallelism.

Keywords-Voltage islands; compiler optimizations; energy consumption; voltage scaling; compiler-based parallelization

Introduction

Power consumption has now become a major constraint in embedded systems design[1][2][19]. Estimating the power consumption for the entire system and its sub components has become an emerging issue in the embedded system design. With the growing needs of increased throughput and bandwith, the processing power is increasing. In this context the role of operating system has come into existence. It offers a wide range of services which eases the exploitation of embedded systems by limiting the hardware so that it can minimize time for designing, development and testing. But the impact of Operating System on the power consumption has not been fully exploited[17][18][9]. Here the focus is on voltage islands and its control domain supported by embedded multiprocessor architecture. Also the mapping of embedded applications onto embedded architecture[18].This paper considers embedded multimedia application codes built from multidimensional arrays of signals and their nested loops[20]. One of the main characteristics of these applications is that an optimizing compiler can analyze patterns of data accesses during compilation then and reconstruct them based upon the optimized result[21]. The power consumption in conventional CMOS circuitry is composed of two sources; dynamic and static power. Power consumption in CMOS circuitry is given in equation1:

….equ1

Static power loss is the power loss due to leakage current flowing between the source and drain and it occurs when transistor is in reverse biased junction.

Dynamic power has two components switching power and short circuit power that is given in below equation

Voltage Islands can be used at different levels of the design hierarchy to increase their effectiveness. A block which can be switched off could exist within a larger block only if it is running at a stable voltage. While constructing a voltage island considering these factors could yield large variety of useful patterns.

V2

V1

VC

V11

V22

switch

switch

logic

logic

Switch

Switch

Power Management Unit

Fig.1 Multi-level Voltage Islands Architecture

These islands develop the threshold design methodology. These islands are created to run a block with active power and low voltage. Here low voltage is considered to be the lowest voltage among the other blocks in the design. During sleep mode the standby power is minimized by shutting down the low voltage blocks.

System Design:

For analyzing power consumption and reduction of compiler directed embedded system, a design of dynamic compiler with DVS is implemented[3]. Here the original code is first compiled. The result after compilation is observed and is executed. Then the optimization is done at runtime.

Monitor and Judger

Original code

Run time Optimization and compiler

Executing the code

First time compiler

OS and Hardware

Fig.2 Overall framework of DVS combined with dynamic compiler

Algorithm for task parallelism in compiler directed embedded system:

Step 1: Input number of processors NP and number of nested loops NL

Step 2: while i <= NL repeat steps 3 to steps 9

Step 3: i=1

Step 4: increment I by 1

Step 5: while i <=NP repeat steps 6 to steps 9

Step 6: set counti = estmiter(Pi)

Step 7: set costi = estmcost(Pi)

Step 8: set wrkldi = counti * costi

Step 9: while i <= n do

Step 10: sort the processors based on their workloads

Step 11: set SP1 = Vmax

Step 12: call Wrkldtime function with argument SP1 and assign the value to Tmax

Step 13: set i=2

Step 14: while i<= Np repeat steps 15 to steps 17

Step 15: if Ti < Tmax

Step 16: set SPi = VL

Step 17: increment i by 1

Step 18: End

Where

Li : Loop nest of i processors

Pi : Processor i

SPi :sorted processors i

wrkldi : Workload of processor i

Ti : execution time of processor i

Wrkldtime: Execution time to complete workload of processor i

Vmax : Highest voltage level

VL : Lowest voltage level

Tmax : Execution time of maximum workload

MIR Code:

1) i=1

2) if i<= NL goto 4

3) i=i+1

4) i=1

5) if i <= Np goto 6

6) Itercounti = estmiter(Pi)

7) Itercosti = estmcost(Pi)

8) wrkldi = itercounti *itercosti

9) i=i+1

10) goto

11) if i<=n goto 13

12) goto 17

13) temp= SPi

14) SPi = SPi+1

15) SPi+1 =temp

16) i=i+1

17) SP1= Vmax

18) Tmax = Wrkldtime(SP1)

19) i=2

20) if i<= Np goto 24

20) if Ti <= Tmax goto 22

21) SPi = VL

22) i=i+1

23) goto 19

24) End

Related work:

[5] proposes a method to solve floor planning problem stimulated by voltage islands in which island partitioning and voltage level assignments are done concurrently to reduce total power consumption. Here the key factors for planning are area and power consumption. [6] proposes a methodology based on facility location problem to improve voltage assignment by incremental placement and outlier detection. [7] proposes a methodology to implement voltage islands and reduce total power consumption under timing constraints with minimal overhead. [4] presents a detailed study of network on chip design for both two and three dimensional system on chip design. [5] presents a system architecture and methodology to reduce static and active power in system-on chip design. [6] proposes an algorithm that develops voltage island boundaries for power against design cost under performance requirements. [11] describes an approach that balances performance and power constraints based on a two dimensional topology with connected graph. [12] proposes a framework for designing system architecture using dynamic compiler.

[13] presents a framework for memory bounded loops.

[14] proposes a methodology using dynamic voltage scaling to implement real time loop scheduling. [15] proposes a methodology to choose the most appropriate voltage/frequency level which can be employed at any time to any communication link. This is done by exploiting the regularities found in data accesses of code with which the communication patterns can be retrieved. [16] proposes a framework to minimizes the resulting time delay in application responses which in turn can exploit the power consumption in voltage islands.

This paper presents a Verilog based methodology to measure the power reduction of a circuit design considering mainly the dynamic power. During the simulation the verilog models determines the possibility of any static levels of the signals. The results obtained are used to calculate the power consumption of the entire system. Prior to power calculation, the netlist of the design is generated. This methodology uses RTL design as input and produces optimized power level netlist. The input is given to HDL compiler initially. For calculating the power reduction, power compiler is used. Simulation generates information about the switching activity of the design and the information is stored in a file. This file contains information from either RTL or from gate level simulation. During optimization the power compiler uses information about switching activity to make decisions. This optimization is achieved only at high level of productivity. In the gate level netlist, for optimization the main constraints considered are area and timing. The result is then compiled using Design compiler. These constraints then generate optimization values. This gate level analysis can be done at many points in the whole system. After optimization the optimized values are compared and a report is generated.

Future Work:

Since the power estimation flow is generated, timing analysis can be performed. Comparison between the optimized values reported using synopsis tools and Cadence tools can be done. Comparison of netlist can be done with other extraction tools. Circuits can be tested in real time using different power measuring devices with same input and the values can be compared.