Cipher And Decipher High Performance Mac Architecture

Published Date: 02 Nov 2017

Abstract.

This paper presents the architecture and implementation of LMAC which is the core block for high speed modem such as HSPA+ and LTE. The required data rate of these modems is 28.8Mbps/11.5Mbps (HSPA Release 7 modem) and 100Mbps/50Mbps (LTE modem) for downlink/uplink, respectively. To support higher data rate, we designed the new LMAC. Architecturally, LMAC includes cipher HW and provides functions such as fast data transfer, packet generation and parsing. Especially, we designed a new function which combines data transfer with cipher and has more performance benefit. As a result, our design can be used for the platform to support HSPA+ LTE modems. And also, we reduced the processing time and the CPU & bus utilization; therefore, SW can obtain more margins to process the protocol stack.

Introduction

In wireless and telecommunication system, higher data rate is necessary due to increasing the usage of multimedia such as music, UCC and so on. Therefore commercialized communication systems (3CPP) III such as NVCDMA and HSDPA/HSUPA are moving to HSPA+ and LTE (Long Term Evolution) which can support higher data rate. Not only the physical throughput but also protocol stack performance should be enhanced to support higher data rate. As data rate is higher, the more performance of MAC (Medium Access Control) layer should be necessary. MAC processor based on WLAN Pi and LMAC (Lower MAC) based on mWiMAX rill are representative examples for increasing data rate. This paper presents the new hardware architecture of MAC which was neglected in 3GPP modem design. In the proposed architecture, the data is efficiently transferred between PHY and CPU. In particular, we integrate cipher H/W to support security Li, Li, IQ into LMAC. This design can reduce memory access time and CPU and bus utilizations. Therefore, a high performance modem can be constructed. This paper is organized as follows. Section M represents the design challenges for the design LMAC architecture, and Section El describes the implementation details of LMAC. Section l discusses the experimental results of LMAC. Finally, section El provides a brief conclusion and a description of future work.

Design Challenges

Basic Requirements

This section describes design challenges of LMAC for HSPA+ and LTE modems. The first and most important goal of LMAC is support of high data rate. The second goal is the design of LMAC platform for both modems. We analyze each modem's requirements and differences, and explain about key features of design choices. HSPA+ modem should support 28.8Mbps/11.5Mbps throughput, downlink/ uplink respectively, and support WCDMA, HSDPA, and HSUPA specifications. The packet formats which must be controlled in the MAC/RLC layer arc various. Each PDU (Protocol Data Unit) size is 320bits or 640bits. When making and controlling these packets, bit operation is necessary because the header is not byte-aligned. Therefore, it is necessary that minimizing these overhead. LTE modern should support 100Mbps/50Mbps throughput, downlink/uplink respectively. Contrary to HSPA+ modem, bit operation is not necessary because the header and payload of packet are byte-aligned. It transmits small number of PDUs, but must support higher data rate. Therefore, LTE modem must have architecture suitable for burst transmissions.

Data Path Design and Cipher HW

3GPP defines the security level provided by UE (User Equipment). And also, it defines the functions and algorithms used in protocol stack. The functions are called cipher in uplink, and decipher in downlink, generally we call cipher. Cipher is processed in the RLC and MAC layer in case of HSPA+, and the PDCP layer in case of LTE. Cipher is divided into f8, data confidentiality function and f9, data integrity function. Kasumi VI and snow 30 algorithms are used in HSPA+, and SNOW 30 and AES algorithms are used in LTE. Basically, cipher is time consuming job. The processing time increases in proportion to the increase of data size. If cipher is implemented with hardware the sequence is as follows. First, 11W reads the data from memory and processes cipher function and then writes to memory. Therefore the total processing time is determined by the performance of cipher algorithm and data access time. Data rate is changed from WCDMA (384Kbps, 20ms TTI) to IISPA+ (28.8Mbps, 2ms TTI) and LTE (100Mbps, lms TTI) in downlink. This means that cipher must process faster about 75 250 times. There are some methods to increase performance of cipher such as using higher clock, cipher core algorithm improvement, and parallelizing cipher core. Also, adding input/output buffer can be used burst data transfer. If every data are saved one buffer, buffer size must be large. Therefore double buffering method can be used. This method reduces not only buffer size but also latency of read or write.

The most important issue in point of architecture is how to design data path. The number of necessary main data path is two (uplink and downlink). Because modem must support uplink and downlink data transmissions simultaneously. From this point of view, it is important that LMAC includes or excludes cipher hardware. Cipher hardware with independent data path can be implemented, because cipher is not dependent on data transmission. But, in case of uplink, data is transferred after ciphering, or in case of downlink, data is transferred after deciphering. In other words, if cipher doesn’t happen simultaneously or time is sufficient to process, data path \yin be shared for saving modem's size. On the other hand, if we can control the sequence of data, we can improve the performance with eliminating the redundant memory access. We will explain detailed in the next section.

SW and HW Partitioning

In 3GPP specification, there are many functions which must be controlled in MAC or RLC layer. So, it is hard to find the HW functions to maximize performance and efficiency. In this paper, we concentrate on functions that consumes more time among data transmission sequence. In case of WCDMA/HSUPA/ HSDPA modem, the header of packet is non byte-aligned. This means that bit operation is necessary when we make or parse the packet. If these are controlled by software, the performance comes down. Therefore, hardware function of packet generation and parsing is efficient to reduce data transmission time. In case of LTE modem, packet sizes are various but these are byte-aligned. Therefore, these HW functions aren't necessarily.

Implementation of LMAC

LMAC Architecture

In this section, the architectures and the implementations of HSPA+ (3GPP release 7) modern and LNIAC of LTE modem are described. LMAC is an abbreviation of Lower MAC that can be defined as a HW accelerator of L2 layer (MAC & RLC H, jai). With the existing software only implementation, it is hard to process high speed data required by HSPA+ and LTE. Therefore, to increase the throughput, the hardware architecture and the various functional blocks including cipher are designed in this paper. Figure II shows a simple diagram of HSPA+ and LTE modems. LMAC is located between CPU memory and PHY. It is responsible for main data path with the AXI bus. The cipher HW in the LMAC processes the cipher function more efficiently than the original method which processed it by the MAC/RLC/PDCP layer.

Figure describes more detailed architecture of LMAC. For convenience, HSPA1 modem and LTE modem are shown together. The grey part represents LTE modem only path. The two modems use the memory interface and commonly use the encoder buffer of the TX path and the decoder buffer of the RX path as the modem PHY interface. Through the AXI bus, LNIAC reads or writes the data to or from the memory and then it reads or writes the data to or from the buffers. For the fast data transmission, LMAC includes the embedded DMA controller (eXDMAC) for the AXI bus. As shown in figure IQ LTE modem has two eXDNIACs which can process simultaneously transfer, cipher and decipher for the uplink and downlink data. In the view of the modem, it has four DMA channels to access the bus. The cipher and decipher are symmetric but the sizes of the input and output buffers are different according to the data rates. All data accesses are performed using the eXDMAC. In the case of LTE modem, the data sizes of cipher and decipher are huge. Therefore, the double buffering method is applied to the input buffer to reduce the buffer size and hide the read latency. In the case of HSPA+ modern, a significant performance enhancement was achieved by write the data to the encoder buffer directly. The detailed explanation of the method will be presented in next section.

Packet Generation and Header Parsing

In case of IISPA+ modem, LMAC processes the some part of MAC/RLC layer function, such as packet generation and header parsing. Packet generation function integrates non byte-aligned headers and byte-aligned payload into packet, and then writes to the encoder. On the contrary, header parsing separates headers and payload from packet, and then writes to the memory. These functions are time consuming work because bit operation must be used. There are many packet formats in MAC layer such as MAC, MAChs, MACe, and MACes. Figure nand figure I show the representative packet formats. The headers must be necessary or can be eliminated in accordance with the channel mapped with PHY. So, packet types are various and complicated. In case of LTE, headers are byte-aligned, so we use scatter/gather operation supported by eXDNIAC. There is no dedicated HW.

Cipher HW

In our implementation, cipher is significant component in terms of architecture and performance. Figure shows the common block diagram of cipher for HSPA+ and LTE modems. Architecturally, cipher core has input and output buffer, and eXDMAC controls data stream to minimize the latency. We will present the method to maximize the performance iii the this section.

Performance Evaluation

Figure El presents the timing diagram of the LMAC operation. The upper part shows the HSPA+ modem and the lower part shows the LTE modem. The left portions show the time of downlink and the right portions show the time of uplink, respectively. The inside operation of LMAC is indicated LMAC, this portion has the fixed time to process. The operation through AXI bus is indicated AX! Bus, it is different in time because of the traffic on AXI bus. We are testing the HSPA+ modem and LTE modem, so the performance is evaluated with RTL simulation. We assume the bus traffic is idle and the remained factors are clock accurate. Base clock is 133MHz and bus interface has 64bit width.

The assumptions for LMAC performance of IISPA+ modem are as follows. Data rate is 11.5/14.4Mbps for uplink/downlink respectively and 1 PDU size is 640bits. This is the base values of HSPA+ Release 6 specification. Our modem support Release 7, but in this section, we use values of Release 6 specification. Because that data rate of Release 7 is higher than that of Release 6, but PDU size is variable and big, and header is byte aligned, therefore SW processing time is lower than that of Release 6. That is, in point of system performance, the overhead of Release 6 is higher than that of Release 7.

Conclusions and Future Works

This paper shows the design and implementation of LMAC architecture for high speed 3GPP modem. We designed the new LMAC architecture which includes cipher HW. Functionally, LMAC processes data transfer, cipher, packet generation and header parsing. These are time consuming jobs if processed by SW. Especially, the function which combines data transfer with cipher increase the performance of LM AC, dramatically. Hereafter, we will design the integrated LMAC, which have both functions of HSPA+ and LTE, and share memory, registers, and control logic. In the near future, two modems are integrated into one chip; therefore, the new LMAC will be the platform supports two modems simultaneously. Furthermore, our architecture can be the base platform for the 4th generation modem.

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