Cam Design For High Speed Low Power Computer Science Essay

Published Date: 02 Nov 2017

VADDI KARTHIK #1, SREENIVASA RAO IJJADA (Asst.professor)*2

Dept. of ECE, GITAM, University

VISAKHAPATNAM, INDIA

[email protected]

[email protected]

Abstract— In the recent emerging applications like space, communications, computers and informatics and bio-medicals, the embedded memories occupy large part of the area in the system on chips (SOCs). Device scaling enhances the chip density and reduces the power consumptions in the chip. But the technology scaling below the 100 nm nodes increases the subthreshold leakage and gate leakages which make the static power more than the dynamic power of the system. Moreover by reducing the supply voltage, both the static and dynamic powers in the memories can be reduced. Ultra-low power SRAM s are very slow and they can’t be used for the high speed applications. Content Addressable memories (CAMs) offers high speed compared to the SRAMs. A low power CAM cell is designed at 90nm technology node using BSIM4 parameters and is made to work at the supply voltage 0.6V to 0.9V, with a power consumption of 0.0579 μW to 0.171 μW at the frequency of 1GHz. The speed is improved by the factor of 10 compared to the previous designs. The simulation is done using Virtuoso CADENCE tools.

Keywords— CAM, search line, bit lines parallel CAM, series CAM , high speed memories, ultra-low power memories, match lines.

Introduction

CAM is a special type of computer memory used in certain very high speed searching applications. It is a fully associative memory with a search time of only one clock cycle unlike the traditional RAMs that requires two or more clock cycles for a search operation and is a class of memory that allows access of data instead of physical address as in the case of SRAM and DRAM. With a more than one tag search per memory access for the RAM-based caches and their lower hit rate, a CAM which consumes for a search, no more than twice the energy consumption of an equivalent RAM can lead to a more energy efficient cache design. One of the techniques to reduce the search current in the match circuits is to use a NAND-type match-line circuit to get a word match signal [1], rather than the NOR-type circuit, [2] which is generally used for speed-oriented CAMs. In the NAND-type match-line technique [3], the match-line driver devices in the cells belonging to a word are connected in series. Not only the NAND-type circuit inherently slower than the NOR-type circuit, but also the former can be much more strongly influenced in the circuit speed than the later by wafer process variations. The subthreshold design provides good power reduction but increase delay [4]. Subthreshold devices performance will not be degraded, but they are very slow compared to the devices operated in the strong inversion region. Therefore subthreshold SRAMs are not suitable for high speed applications

BASIC CAM

Basically CAM is of two types - binary CAM and ternary CAM (TCAM). Binary CAM is primarily used as instruction or data cache while ternary CAM has an additional "don’t-care state" and is mainly used for the longest prefix matching tasks in network search engines. The basic CAM cell architecture is shown in the figure-1. Its structure is similar to that of the normal RAM and is implemented by comparison circuits along with bit storage. The traditional CAM cell requires 9 transistors in standard CMOS logic design style. Each cell within the CAM has the same basic structure of a 6T SRAM cell. Another three more transistors for comparing the bit that is stored in the cell is matched or not. The comparison circuitry varies depending on the design and the implementation. The sense amplifiers and latches provide an interface to give out the result of the search. The signal Pre is used to control pre-charging the match-lines. The address decoder is used for writing original data to CAM cells.

The operation of basic CAM follows read, write, standby and comparison operations [5].

Fig. 1 Basic CAM cell circuit

Since it has high speed of operation compared to the other memories, to utilize this advantage of CAM a lot of research is going on towards the reduction of the power consumption in the CAM.

Low power cam cell design methodology

In this paper, we proposed some novel techniques to reduce the power consumption due to hardware complexity and energy loss per each search as the number of simultaneous searching operations are more at the circuit level. The results are compared with open literature.

Design Method-1

In this methodology, the low power CAM cell is designed by adopting the technique in the paper [6]. The proposed CAM is shown in the figure-2. In this proposed CAM cell, gating transistors are used, where the transistors M2 and M4 are HVT NMOS transistors and transistors M5 and M7 are HVT PMOS transistors.

Write mode: When the signal word line (WL) is asserted, the access transistors M10 and M9 are made ON and the data given at BL and are stored in to the cell. Assume that the data written on to the cell is logic ‘1’ the transistor M3 is ON connecting the gate of HVT transistor M2 to ground and allowing it to ON and pulling down the node towards logic ‘0’. As the width of the transistors M4 and M3 are half compared to nominal CAM cell and the resistance path will be larger in the proposed CAM cell [7]. The flow of subthreshold current in the subthreshold region of operation is reduced making the static power dissipation to be minimized and allowing the overall power dissipation to be reduced.

Fig. 2: Proposed CAM cell-1 circuit

Read mode: Before read operation the BLs are precharged to VDD and asserting the WL to be active, the stored value in the cell is read on the Bl. Assume that the stored value is ‘0’ then the transistors M6 is made on and allowing the HVT transistor M5 On pulling the node to the logic ‘1’ then the precharged value at the BL will be pulled down to ground indicating the value stored in the cell is logic ‘0’.

Match mode: In this case the access transistors M10 and M9 are OFF and the cell will be in latch mode and the match line (ML) signal has to be precharged to VDD initially before operation. The data and switches ON the transistors M11 and M12 and based on comparison of data with the stored value, the signal activates the transistor M13 changing the value of ML. This method offers some drawbacks.

i) The voltage levels of the ML are degraded with difference of 0.4V.

ii) Need to use the buffering technique in order to overcome the drawback.

This method is suitable for low power and high speed applications, as the voltage swing is reduced. In this method, as the width of the transistors are reduced compared to the conventional method, the path resistance between VDD and ground increases when the transistors comes to transition region. Thereby the leakage current through the off transistors reduces. This technique reduces the output voltage swing due to the threshold voltage loss caused by the additional MOS transistors. The simulation waveforms of the CAM with this method is shown in the figure-3

Design Method-2

To re-gain the full voltage swing which lost in the above method at its output, the circuit is modified by adding two inverters at the output node. These two inverter functions would "cancel" each other so that there would be no inversion from input to the final output. While this may seem like a pointless thing to do, it does have practical application. A weak signal source may be boosted by means of two inverters. The logic level is unchanged, but the full current-sourcing or sinking capabilities of the final inverter are available to drive a load resistance if needed. By using both the techniques at once the voltage swing is regained again and power dissipation is reduced by only 40%. The simulation waveforms of the CAM with this method are shown in the figure-4. This method is suitable for the full swing voltage applications but the transistor count and power consumption increases seriously.

Design method-3

In this design method, to reduce the power, transistors count and delay, the positioning of the HVT and standard VT transistors are interchanged in the method -2 to form method-3. The simulation waveforms of the CAM with this method are shown in the figure-5.

simulation results

Fig. 3 shows the simulation results of basic CAM cell and it is observed that the power consumption is 47μw and delay is 0.12 nsec at the supply voltage of 1v. Fig. 4 shows the simulation results of the CAM cell designed with methodology 1 and it is observed that the power consumption is 5.14μw and the delay is 0.139 nsec. Fig. 5 represents simulation results of the CAM cell designed with methodology 2 and it is observed that the power consumption is 13.49μw and the delay is 1.019 nsec. Fig. 6 shows the simulation results of the CAM cell using methodology 3 and it is observed that the power consumption is 0.017μw and the delay is 0.212 nsec.

Fig. 3 Simulation waveforms of basic CAM cell

Fig. 4. Simulation waveforms of design method-1 CAM cell

Fig. 5 Simulation waveforms of design method-2 CAM cell

Fig. 6. Simulation waveforms of design method-3 CAM cell

results comparisons

Fig. 7. Power comparisons of basic cell and method 1 cell

Fig. 7 shows the power comparison results of method 1 CAM cell with the basic cell for supply variation of 400mv to 1v. It is observed that the method 1 cell consumes very less power and its delay is little bit more compared to basic cell.

Fig. 8. Power comparisons of method1 and method 2 cells

Fig. 8 shows the power comparison results of method 1 and method 2 cells for supply variation of 400mv to 1v. It is observed that the method 1 cell consumes very less power.

Fig. 9. Power comparisons of method 1 and method 3 cells

Fig. 9 shows the power comparison results of method 1 and method 3 cells for supply variation of 400mv to 1v. It is observed that the method 3 cell consumes very less power.

Fig. 10. Delay comparisons of all the proposed cells with basic cell

Fig. 10 shows the delay comparison of all proposed cells with the basic cell and it is observed that basic and method-1cells offers less delay when compare method-2 and method-3 cells. There is always a tradeoff between power consumption and delay. A hybrid-type CAM design which aims to combine the performance advantage of the NOR-type CAM with the power efficiency of the NAND-type CAM. The hybrid-type CAM provides a fast pull-down path to speed up the lightweight match line discharge, the search performance of our design is even better than that of the traditional NOR-type CAM[8]. To further reduce power consumption, we can implement pipelined SL architecture. We divided the CAM array into pipeline stages in the direction of the search-word distribution. Once a match is detected in a pipeline stage, this architecture turns off the remaining stages thus saving power[9]. About half the energy consumed in a CAM is due to the repeated precharging and discharging of all but one of the match lines in each access. This is due to the "parallel" (or NOR type) implementation of the match operation. "Serial" (or NAND type) CAM design search one bit at a time (for each row) so that they do not discharge a single large capacitance when there is no match. Unfortunately, they are generally slower than parallel CAMs, as their search speed depends on the number of cells in a row[10].

Conclusions

From the results, it is observed that from the three new design methods, the CAM designed with the methodology-1 consumes 5.143 μW power, the CAM designed with the methodology-2 consumes 13.49 μW power and the CAM designed with the methodology-3 consumes 0.0178 μW power. All the simulations are performed at the frequency of 1GHz.

From this, it is concluded that the method-1 supports for the low power applications, method-2 is suitable for the high speed applications and the method-3 accommodates both low power and high speed applications. The CAM with the low power peripherals further reduces power requirement.

Acknowledgment

The authors are thankful to VLSI Cadence laboratory people and also to GIT, GITAM University for providing the slots to research this paper.