Hardware Simualtion And Synthesis Using Cpld

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02 Nov 2017

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Hardware

Simualtion

and

Synthesis

Using

CPLD

Design

and

VHDL

D.

L.

N.

M.

Hettiarachchi

February

19,

2013

Abstract

This

Report

contains

several

practical

experiments

which

extend

from

basic

to

somewhat

advance

level,

and

here

CPLDs

are

Programmed

and

Synthesized

by

using

VHDL

and�Xilinx

ISE

Design

Suite�

and

it

was

Simulated

by

using

�Altera

ModelSIM�

simulator.

Contents

List

of

Figures

3

List

of

Tables

5

1

Introduction

6

1.1

Overview

.........................................

6

1.2

Objectives.........................................

6

1.3

OrganizationOfTheReport...............................

6

2

Materials

and

Methods

7

2.1

Materials

.........................................

7

2.1.1

CPLD.......................................

7

2.1.2

CPLDProgrammingBoard

...........................

10

2.1.3

XilinxISEDesignSuite

.............................

10

2.1.4

AlteraModelSim

.................................

11

2.2

Methods..........................................

12

3

Practical

Experiments

15

3.1

Experiment1:

Synthesizea2-inputANDgate

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

15

3.1.1

Theory

......................................

15

3.1.2

Procedure.....................................

16

3.1.3

ResultsandObservation.............................

17

3.2

Experiment

2

:

Designing

a

BCD

to

SSD

Decoder

Using

Schematic

Design

Method

18

3.2.1

Theory

......................................

18

3.2.2

Procedure.....................................

19

3.2.3

ResultsandObservation.............................

23

3.3

Experiment

3

:Designing

a

BCD

to

SSD

Decoder

Using

VHDL

Programming

Method

25

3.3.1

Theory

......................................

25

3.3.2

Procedure.....................................

25

3.3.3

ResultsandObservation.............................

26

3.4

Experiment

4

:

Add

a

Digit

Test

Button

to

The

BCD

to

SSD

Decoder

(VHDL

Method).

.........................................

28

3.4.1

Theory

......................................

28

3.4.2

Procedure.....................................

28

3.4.3

ResultsandObservation.............................

29

3.5

Experiment

5

:

Designing

a

BCD

to

SSD

Decoder

Using

VHDL

Programming

(TruthtableMethod).

..................................

30

3.5.1

Theory

......................................

30

3.5.2

Procedure.....................................

30

3.5.3

ResultsandObservation.............................

31

3.6

Experiment

6

:

Implementation

Of

Sequential

Logic

Using

VHDL

Programming

.

32

1

3.6.1

Theory

......................................

32

3.6.2

Procedure.....................................

33

3.6.3

ResultsandObservation.............................

34

3.7

Experiment

7

:

A

State

Machine

Using

VHDL

Programming-(

MOD10

Counter

).

35

3.7.1

Theory

......................................

35

3.7.2

Procedure.....................................

36

3.7.3

ResultsandObservation.............................

37

3.8

Experiment8:SynthesisofComponents

.......................

40

3.8.1

Theory

......................................

40

3.8.2

Procedure.....................................

40

3.8.3

ResultsandObservation.............................

41

4

Discussion

and

Conclusion

43

4.1

Discussion.........................................

43

4.2

Conclusion

........................................

44

Bibliography

44

5

Appendix

46

5.1

ShortQuestionandAnswers...............................

46

List

of

Figures

2.1

XC9572CPLDChip

...................................

7

2.2

BlockDiagramofXC9572CPLDArchitecture

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

8

2.3

FunctionBlock

......................................

8

2.4

XC9500XLMacrocellWithinFunctionBlock

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

9

2.5

CPLDProgrammingBoard

...............................

10

2.6

XilinxISEGUI......................................

10

2.7

Synthesizingprocesscompleted

.............................

11

2.8

Objectwindowofthesimulator.

............................

11

2.9

NewProjectWizard

...................................

12

2.10CPLDdetailsforthenewproject............................

13

2.11Addnewsourcetype...................................

13

2.12Addmoduletype.....................................

14

3.1

SymbolandtheTruthTableofANDGate.......................

15

3.2

Schematicdiagramof2-inputANDGate.

.......................

16

3.3

I/OPinassignment....................................

16

3.4

TopViewoftheCPLD:I/OpinsindicatedbyBluecolor.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

16

3.5

AND

Gate

Truth

Table

varification

using

switches

and

LEDs.

.

.

.

.

.

.

.

.

.

.

.

.

17

3.6

BCDtoSSDdecoderblockdiagram

..........................

18

3.7

CommonAnodeSSDConfiguration

..........................

18

3.8

"g"segmentSchematicDesign..............................

19

3.9

"g"segmentoutputdisplayedontheSSD

.......................

20

3.10SchematicdiagramforcompleteSSD

.........................

21

3.11

I/OPinassignmentoftheBCDtoSSDdecoder

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

22

3.12

TopViewfloorplanandthelegendoftheCPLD

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

22

3.13

(part-a)

-Results

of

the

BCD

to

SSD

decoder

while

varying

input(switches).

.

.

.

23

3.14

(part-b)

-Results

of

the

BCD

to

SSD

decoder

while

varying

input(switches).

.

.

.

24

3.15VHDLcodeforBCDtoSSDdecoder.

.........................

25

3.16

SimulatedOutputoftheBCDtoSSDdecoder.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

26

3.17

(Results

of

the

BCD

to

SSD

decoder

while

varying

input(switches).

.

.

.

.

.

.

.

.

.

27

3.18

VHDLcodeforDigittestbuttonofBCDtoSSDdecoder.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

28

3.19PinassignmentfortheDigitTest............................

28

3.20

Digit

Test

:

initially

SSD

showing

"1",

when

Digit

test

button

Pressed

SSD

shows

"8"

29

3.21

Digit

Test

:

initially

SSD

showing

"0",

when

Digit

test

button

Pressed

SSD

shows

"8"

29

3.22

VHDLcodeforBCDtoSSDdecoderusingtruthtable

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

30

3.23

PinassignmentfortheBCDtoSSDdecoder

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

30

3.24

part-a

:BCD

to

SSD

decoder

using

VHDL

truth

table

method.

.

.

.

.

.

.

.

.

.

.

.

31

3.25

part-b

:BCD

to

SSD

decoder

using

VHDL

truth

table

method.

.

.

.

.

.

.

.

.

.

.

.

31

3.26TimingDiagramOftheDFlipFlop

..........................

32

3.27

BottomLEDactasaClockStateIndicator

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

33

3.28VHDLCodeforDFF...................................

33

3.29PinassignmentoftheDFF

...............................

34

3.30

OutputofaDFlipFlopdevicewhenvaryinginput.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

34

3

3.31

StateDiagramofamod10counterwithenableandreset

.

.

.

.

.

.

.

.

.

.

.

.

.

.

35

3.32

VHDLcodeoftheMod10counterwithenableandreset.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

36

3.33PinassignmentoftheMod10counter

.........................

36

3.34a:Wavepatternofthemod10counter

........................

37

3.35b:Wavepatternofthemod10counter

........................

37

3.36a:Resultsofthemod10counter.............................

38

3.37b:Resultsofthemod10counter.............................

39

3.38WhenResetisactive...................................

39

3.39Componentaddedtothemainfile

...........................

40

3.40

VHDL

code

of

the

Counter

to

SSD

decoder

with

enable

and

reset.

.

.

.

.

.

.

.

.

.

40

3.41

PinassignmentoftheCountertoSSDdecoder

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

41

3.42ResultsoftheCountertoSSDdecoder.

........................

41

3.43WhenResetisactive...................................

42

5.1

StatediagramofaJKflip-flop

.............................

47

5.2

VHDLcodeofthe8-bitJonsoncounter.

........................

47

4

List

of

Tables

3.1

TruthTableOFBCDtoSSDDecoder.........................

19

3.2

TruthTableOfTheDFlipFlop

............................

32

5

Chapter

1

Introduction

1.1

Overview

Different

types

of

logic

devices

which

allows

process

to

be

automated

are

widely

used

in

hardware

systems

in

almost

every

field

of

work,

which

vary

from

basic

level

to

very

large

scale

hardware

development.

When

it

comes

to

large

scale

hardware

designs,

Simulation

and

Synthesizing

take

place

a

vital

part

of

the

process.

CPLD

(Complex

Programmable

Logic

Devices)

are

used

to

develop

complex

hardware

and

to

achieve

this

complexity

CPLD

contains

configurable

logic

blocks.

VHDL

Programming

language

is

used

in

order

to

program,

synthesize

and

simulate

CPLDs.

VHDL

stands

for,

VHDL

=

VHSIC

Hardware

Description

Language.

VHSIC

=

Very

High

Speed

Integrated

Circuit.

CPLD

logic

blocks

can

configure

using

schematic

diagrams,

logic

equations,

truth

tables

or

VHDL,

in

order

to

perform

desired

logical

function

of

the

system.

1.2

Objectives

In

general

the

main

objectives

of

these

practicals

was

to

acquire

a

good

knowledge

and

experience

in

programming

,

synthesizing

and

simulating

logic

devices

using

VHDL

and

also

a

very

good

knowledge

about

CPLDs

and

their

applications

are

expected

to

be

gained.

1.3

Organization

Of

The

Report

The

report

is

divided

into

5

chapters,

which

each

chapter

explaining

different

aspects

in

detail,

Chapter

1

:

Basic

introduction

about

this

report

and

its

contents.

Chapter

2

:

Theoretical

background

and

information

about

materials

and

methods

which

used

to

implement

are

discussed

Chapter

3

:

Practical

Experiment

details

with

step

by

step

are

included

Chapter

4

:

Overall

discussion

with

difficulties

occurred

during

experiments

and

final

conclusion

6

Chapter

2

Materials

and

Methods

2.1

Materials

2.1.1

CPLD

In

these

practical

experiments

Xilinx

XC9572

Programmable

CPLD

was

used

which

operates

in

+

3.3

V

supply

voltage.

following

figure

2.1

shows

XC9572

CPLD

PLCC

(Plastic

Leaded

Chip

Carrier)

package

type

.

Figure

2.1:

XC9572

CPLD

Chip

Features

of

CPLDs,

�

Cental

global

interconnect

�

Simple,

deterministic

timing

�

Easily

routed

�

PLD

tools

add

only

interconnect

�

Wide,

fast

complex

gating

A

Complex

Programmable

Logic

Device

(CPLD)

is

a

combination

of

a

Function

blocks

(logic

blocks)

which

contains

bank

of

macrocells

like

SPLD(Simple

Programmable

Logic

Devices-usually

PALs)

and

Input/Output

Blocks(IOBs),

they

all

are

interconnected

with

programmable

switch

matrix

called

global

interconnection

matrix.

Because

of

this

matrix

CPLD

can

be

program

in

two

ways:

each

Function

blocks(FB)

can

be

programmed,

and

then

the

interconnections

between

the

FB

can

be

programmed.

Following

Figure

2.2

given

below

shows

the

architecture

of

the

CPLD

as

a

block

diagram.

7

Figure

2.2:

Block

Diagram

of

XC9572

CPLD

Architecture

Each

Function

Block(FB),

as

shown

in

Figure

2.3

is

comprised

of

18

independent

macrocells,

FB

also

receives

global

clock,

output

enable,

and

set/reset

signals.

The

FB

generates

18

outputs

that

drive

the

switch

matrix.

These

18

outputs

and

their

corresponding

output

enable

signals

also

drive

the

IOB.

Logic

within

the

FB

is

implemented

using

a

sum

of

products

representation,

these

product

terms

can

be

allocated

to

each

macrocell

by

the

product

term

allocator.

Figure

2.3:

Function

Block

8

Five

direct

product

terms

from

the

AND-array

are

available

for

use

as

primary

data

inputs

(to

the

OR

and

XOR

gates)

to

implement

combinatorial

functions,

or

as

control

inputs

including

clock,

clock

enable,

set/reset,

and

output

enable.

The

product

term

allocator

associated

with

each

macrocell

selects

how

the

five

direct

terms

are

used.The

macrocell

register

can

be

configured

as

a

D-type

or

T-type

flip-flop,

or

it

may

be

bypassed

for

combinatorial

operation.

Each

register

supports

both

asynchronous

set

and

reset

operations.

During

power-up,

all

user

registers

are

initialized

to

the

user-defined

preload

state

(default

to

0

if

unspecified).

The

macrocell

and

associated

FB

logic

is

shown

in

Figure

2.4.

Figure

2.4:

XC9500XL

Macrocell

Within

Function

Block

9

2.1.2

CPLD

Programming

Board

CPLD

Programming

Board

with

�XC9572

CPLD

PC44�

was

used

in

these

experiments

and

the

CPLD

was

programmed

by

using

parallel

connector.

This

Board

contains

connectors

which

can

use

as

Input/Output

to

the

device

and

also

it

contains

SSD

units

and

several

LEDs

for

check

the

experimental

output.

Following

figure

shows

the

programming

board

that

used.

Figure

2.5:

CPLD

Programming

Board

2.1.3

Xilinx

ISE

Design

Suite

Xilinx

ISE

is

a

powerful

design

suite

which

can

synthesize

and

program

CPLDs,FPGAs,

etc...figure

2.6

given

below

shows

the

GUI

of

the

�Xilinx

ISE�.

Figure

2.6:

Xilinx

ISE

GUI

10

After

done

implementing

designing

the

hardware

(Schematic

or

VHDL

programming

-refer

section

2.2)

Xilinx

ISE

Design

Suite

used

for

synthesize

the

hardware.

Following

figure

shows

how

it

looks

like

when

synthesizing

process

completed

successfully.

Figure

2.7:

Synthesizing

process

completed

2.1.4

Altera

ModelSim

This

is

the

simulator

which

used

in

these

practicals.

This

software

is

very

user

friendly

and

gives

more

options

when

simulating

the

digital

designs,

and

using

this

anyone

can

easily

find

out

about

timing

errors

in

digital

designs.

Although

the

final

result

of

this

software

is

not

exactly

accurate

because

its

a

simulator

and

its

only

checks

the

ideal

conditions

of

the

designs

but

using

this

simulator

we

can

get

a

good

idea

about

designs

and

its

timing

errors.

Steps

are

simple

here,

first

we

need

to

create

�new

project�.

�new

file�)�Add

existing

File�(

existing

VHDL

code

file

).

�compile

all�

option

finally

�simulate�

option.

Then

it

gives

the

Object

window

where

it

contains

the

variable

of

the

design,

and

choosing

what

variable

we

use

and

creating

the

wave

patterns

for

knowing

variable

(inputs)

and

after

that

simulating

the

design

gives

the

output

wave

patterns

for

specified

time

frame.

Figure

2.8

shows

the

object

window

of

the

simulator.

Figure

2.8:

Object

window

of

the

simulator.

11

2.2

Methods

There

are

two

main

hardware

design

methods

were

used

in

these

practical

experiments,

1.

Schematic

design

type.

2.

HDL

programming

type.

Design

type

can

be

choose

selecting

�Top-Level

Source

Type�

from

the

�New

Project

Wizard�

window,

Figure

2.9

shows

�New

Project

Wizard�

window.

Figure

2.9:

New

Project

Wizard

After

selecting

�Top-Level

Source

Type�,

then

CPLD

device

was

specified

in

the

�New

Project

Wizard�

window.

Figure

2.10

below

shows

the

specified

CPLD

details

for

these

experiments.

12

Figure

2.10:

CPLD

details

for

the

new

project

After

selecting

CPLD

details

for

project,

new

Source

file

was

added

to

the

project

using

�New

Source

Wizard�.In

here

again

we

can

choose

the

source

type

as

a

�Schematic�

or

�VHDL

Module�.

Selecting

�Schematic�

as

source

type

directly

brings

up

the

design

window

and

Selecting

�VHDL

Module�

as

source

type

brings

the

�Define

Module�

window,

where

Inputs

and

Outputs

of

the

CPLD

can

define

initially,

although

these

Input

s

and

Outputs

can

edit

again

in

HDL

coding

window.

Following

Figure

2.11

and

Figure�2.12

shows

�New

Source

Wizard�

and

�Define

Module�

window

respectively.

Figure

2.11:

Add

new

source

type

13

(a)

Add

module

type

Figure

2.12:

Add

module

type

After

selecting

proper

method

each

experiment

synthesized,

simulated

and

verified

by

using

�CPLD

Programming

Board�

(

refer

section

2.1.2

)

and

carried

out

separately,

refer

chapter

3

for

more

information

about

methods

and

respective

experiments.

14

Chapter

3

Practical

Experiments

3.1

Experiment

1

:

Synthesize

a

2-input

AND

gate

3.1.1

Theory

The

AND

Gate

is

a

basic

logic

gate,

which

gives

a

HIGH

(1)

output

when

both

inputs

(every

input)

is

LOW

(0).

Following

figure

shows

the

symbol

and

the

Truth

Table

of

the

AND

Gate.

Figure

3.1:

Symbol

and

the

Truth

Table

of

AND

Gate

Boolean

equation

of

the

AND

Gate

is,

A

�

B

=

Output

(3.1)

In

this

experiment

was

carried

out

using

Schematic

design

type

method

(refer

section

2.2

for

more

info

about

methods).

15

3.1.2

Procedure

1.

2-input

AND

Gate

was

synthesized

by

using

Xilinx

ISE.

First

source

type

was

selected

as

schematic

type

and

CPLD

details

were

specified

as

mention

in

above

(Figure

2.10)

and

then

AND

Gate

schematic

was

designed.

Figure

below

shows

the

Schematic

diagram

of

AND

Gate.

Figure

3.2:

Schematic

diagram

of

2-input

AND

Gate.

After

completing

implementing

part,

design

was

synthesized

and

programming

file

was

generated.

2.

Pins

for

the

Gate

were

assigned

using

user

constrain

file.

CPLD

has

lot

of

pins

that

can

act

as

a

input

or

output,

so

the

specifying

gate

pins

properly

using

�user

constrain

file�

easier

than

connecting

it

for

random

pins.

Figure

3.3

shows

about

I/O

Pin

assignment

and

Figure

3.4

shows

the

Top

View

floor

plan

of

the

CPLD.

Figure

3.3:

I/O

Pin

assignment

Figure

3.4:

Top

View

of

the

CPLD:

I/O

pins

indicated

by

Blue

color.

3.

Correct

behavior

was

verified

by

using

switches

and

LEDs

on

CPLD

Programming

Board.

16

3.1.3

Results

and

Observation

After

done

synthesizing

and

generating

HDL

code

for

CPLD,

Programming

Board

used

to

connect

I/O

of

the

AND

Gate

to

switches

and

LEDs.

Figure

3.5

shows

the

obtained

results

of

the

AND

Gate

while

varying

input(switches)

according

to

truth

table.

(a)

Both

low

input:

low

output

(b)

low

and

high

input:

low

output

(c)

high

and

low

input:

low

output

(d)

Both

high

input:

high

output

Figure

3.5:

AND

Gate

Truth

Table

varification

using

switches

and

LEDs.

17

3.2

Experiment

2

:

Designing

a

BCD

to

SSD

Decoder

Using

Schematic

Design

Method

3.2.1

Theory

A

decoder

is

a

device

which

converts

binary

code

data

at

its

input(2-bit,

3-bit

or

4-bit)

into

multiple

output

(2n)

one

at

a

time.

Input

n-bit

decoder

has

2n

output

lines,

Figure

3.6

shows

the

BCD

to

SSD

decoder

block

diagram.

Figure

3.6:

BCD

to

SSD

decoder

block

diagram

SSD

units

have

two

configurations,

1.

Common

Anode

2.

Common

Cathode,

Here

in

this

experiment,

Common

Anode

SSD

was

used,

Following

Figure

3.7

shows

the

Common

Anode

SSD.

Figure

3.7:

Common

Anode

SSD

Configuration

18

so

in

this

experiment

to

create

BCD

to

SSD

decoder

input

was

choose

as

4-bit

it

gives

4-to-16

line

configurations.

Since

here

using

BCD

decoder

binary

number

patterns

of

1010

through

to

1111

not

valid

because

BCD

number

range

is

0

to

9.

Table

below

shows

the

Truth

table

of

BCD

to

SSD

decoder

it

only

contains

valid

number

patterns

only.

Table

3.1:

Truth

Table

OF

BCD

to

SSD

Decoder

BCD

Inputs

Segment

outputs

Display

A

B

C

D

a

b

c

d

e

f

g

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

1

0

1

1

0

0

0

0

1

0

0

1

0

1

1

0

1

1

0

1

2

0

0

1

1

1

1

1

1

0

0

1

3

0

1

0

0

0

1

1

0

0

1

1

4

0

1

0

1

1

0

1

1

0

1

1

5

0

1

1

0

0

0

1

1

1

1

1

6

0

1

1

1

1

1

1

0

0

0

0

7

1

0

0

0

1

1

1

1

1

1

1

8

1

0

0

1

1

1

1

0

0

1

1

9

3.2.2

Procedure

1.

First

single

segment(�g�

segment

-refer

Table

3.1

for

bit

pattern)

of

the

SSD

was

implemented

using

schematic

design

method,then

it

was

Synthesized

and

verified

by

using

programming

board.

Figure

3.8

below

shows

the

schematic

diagram

of

the

�g�

segment.

Figure

3.8:

"g"

segment

Schematic

Design

19

Following

Figure

3.9

shows

the

output

of

the

�g�

segment.

Figure

3.9:

"g"

segment

output

displayed

on

the

SSD

Boolean

logical

expression

for

all

other

including

�g�

segment

of

the

SSD

was

simplified

by

using

�Karnaugh

map

(K-map)�

technique.

20

2.

Then

the

schematic

diagram

for

whole

SSD

was

designed.Following

Figure

3.10

shows

the

schematic

diagram.

Figure

3.10:

Schematic

diagram

for

complete

SSD

21

3.

The

I/O

pin

assignment

of

the

CPLD

was

specified

using

user

constrain

file.

Figure

3.11

shows

about

I/O

Pin

assignment

and

Figure

3.12

shows

the

Top

View

floor

plan

of

the

CPLD.

Figure

3.11:

I/O

Pin

assignment

of

the

BCD

to

SSD

decoder

Figure

3.12:

Top

View

floor

plan

and

the

legend

of

the

CPLD

4.

Correct

behavior

was

verified

by

using

switches

and

SSD

on

CPLD

Programming

Board.

22

3.2.3

Results

and

Observation

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

BCD

to

SSD

decoder

to

switches

and

SSD.

Figure

3.13

and

Figure

3.14

shows

the

obtained

results

of

the

BCD

to

SSD

decoder

while

varying

input(switches)

according

to

truth

table(Table

3.1).

(a)

switches

input

:

0000

(b)

switches

input

:

0001

(c)

switches

input

:

0010

(d)

switches

input

:

0011

(e)

switches

input

:

0100

(f)

switches

input

:

0101

Figure

3.13:

(part-a)

-Results

of

the

BCD

to

SSD

decoder

while

varying

input(switches).

23

(a)

switches

input

:

0110

(b)

switches

input

:

0111

(c)

switches

input

:

1000

(d)

switches

input

:

1001

Figure

3.14:

(part-b)

-Results

of

the

BCD

to

SSD

decoder

while

varying

input(switches).

24

3.3

Experiment

3

:Designing

a

BCD

to

SSD

Decoder

Using

VHDL

Programming

Method

3.3.1

Theory

In

this

experiment

decoder

was

created

by

using

VHDL

programming

method(Refer

Section

3.2.1

for

more

info

about

BCD

decoder

and

SSD).

3.3.2

Procedure

1.

First

BCD

to

SSD

decoder

was

designed

by

using

VHDL

programming.

Figure

3.15

shows

the

VHDL

code.

(b)

part-b(

a)

part-a-

Figure

3.15:

VHDL

code

for

BCD

to

SSD

decoder.

2.

VHDL

design

code

was

simulated

by

using

ModelSim

and

its

behavior

was

verified

(Refer

Section

3.3.3

for

more

information).

3.

The

I/O

pin

assignment

of

the

CPLD

was

specified

using

user

constrain

file.

4.

Device

was

synthesized

and

behavior

was

verified

using

programming

board.

25

3.3.3

Results

and

Observation

1.

Following

Figure

3.16

shows

the

Simulated

Output

of

the

BCD

to

SSD

decoder.

(b)

Displaying

number

�2�

on

the

SSD

(a)

Displaying

number

�1�

on

the

SSD

(c)

Displaying

number

�7�

on

the

SSD

Figure

3.16:

Simulated

Output

of

the

BCD

to

SSD

decoder.

26

2.

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

BCD

to

SSD

decoder

to

switches

and

SSD.

Following

Figure

3.17

shows

Observed

results

of

the

BCD

to

SSD

decoder.

(a)

switches

input

:

0001

(b)

switches

input

:

0001

(c)

switches

input

:

0110

(d)

switches

input

:

0111

Figure

3.17:

(Results

of

the

BCD

to

SSD

decoder

while

varying

input(switches).

27

3.4

Experiment

4

:

Add

a

Digit

Test

Button

to

The

BCD

to

SSD

Decoder

(VHDL

Method).

3.4.1

Theory

The

function

of

the

digit

test

button

is

when

its

pressed,

to

illuminate

all

the

digits

disregarding

the

other

inputs.

Refer

Section

3.2.1

for

more

information

on

BCD

to

SSD

decoder.

3.4.2

Procedure

1.

First

BCD

to

SSD

decoder

was

designed

by

using

VHDL

programming.

Figure

3.18

shows

the

VHDL

code.

(a)

part-a(

b)

part-b-

Figure

3.18:

VHDL

code

for

Digit

test

button

of

BCD

to

SSD

decoder.

2.

Design

was

synthesized

and

user

constrains

were

added

to

the

design.

Following

Figure

3.19

shows

the

pin

assignment

of

the

design.

Figure

3.19:

Pin

assignment

for

the

Digit

Test

28

3.4.3

Results

and

Observation

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

BCD

to

SSD

decoder

to

switches

and

SSD

and

also

Digit

Test

Button

also

connect

to

the

CPLD.

Following

Figure

3.20

and

Figure

3.21

shows

Observed

results

of

the

Digit

Test

of,

the

BCD

to

SSD

decoder.

Figure

3.20:

Digit

Test

:

initially

SSD

showing

"1",

when

Digit

test

button

Pressed

SSD

shows

"8"

Figure

3.21:

Digit

Test

:

initially

SSD

showing

"0",

when

Digit

test

button

Pressed

SSD

shows

"8"

29

3.5

Experiment

5

:

Designing

a

BCD

to

SSD

Decoder

Using

VHDL

Programming

(Truth

table

Method).

3.5.1

Theory

In

this

experiment

decoder

was

created

by

using

VHDL

programming

method(Refer

Section

3.2.1

for

more

info

about

BCD

decoder

and

SSD).

But

this

experiment

uses

truth

table

data

to

implement

logic

equations,

normally

VHDL

can

easily

transform

truth

table

data

to

HDL

this

way

using

VHDL

programming,

even

complex

circuits

can

be

implemented

much

more

easily.

3.5.2

Procedure

1.

First

decoder

was

designed

by

using

VHDL

truth

table

method,Following

Figure

3.22

shows

the

VHDL

code.

Figure

3.22:

VHDL

code

for

BCD

to

SSD

decoder

using

truth

table

2.

Then

design

code

was

synthesized

and

user

constrains

were

added

for

the

design.

Following

Figure

3.23

shows

the

pin

assignment

of

the

design.

Figure

3.23:

Pin

assignment

for

the

BCD

to

SSD

decoder

30

3.5.3

Results

and

Observation

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

BCD

to

SSD

decoder

to

switches

and

SSD.

Following

Figure

3.24

and

Figure

3.25

shows

Observed

results

of

the

Digit

Test

of,

the

BCD

to

SSD

decoder.

(a)

switches

input

:

0000

(b)

switches

input

:

0001

Figure

3.24:

part-a

:BCD

to

SSD

decoder

using

VHDL

truth

table

method.

(a)

switches

input

:

0111

(b)

switches

input

:

1001

Figure

3.25:

part-b

:BCD

to

SSD

decoder

using

VHDL

truth

table

method.

31

3.6

Experiment

6

:

Implementation

Of

Sequential

Logic

Using

VHDL

Programming

3.6.1

Theory

So

far

in

this

report

all

experiments

was

regarding

combinational

logic

devices

only

difference

was

each

experiment

use

a

different

approach

(different

method)

to

get

a

out

put,

From

now

on

practical

experiments

deal

with

sequential

logic

devices

with

VHDL

programming.

In

this

experiment,

D-Filp-Flop

(DFF)

was

implemented

Using

VHDL.

DFF

is

know

as

a

data

or

delay

flip-flop,

DFF

captures

the

data

input

value

when

clock

signal

activate

(rising

edge

or

falling

edge),

In

this

experiment

rising

edge

of

the

clock

signal

was

used

to

activate

DFF.

Following

Table

3.2

shows

The

Truth

Table

of

the

DFF.

Table

3.2:

Truth

Table

Of

The

D

Flip

Flop

Clock

D

Qnext

Rising

Edge

0

0

Rising

Edge

0

0

Non

Rising

Edge

X(dontcare)

Q

Figure

3.26

shows

the

timing

diagram

of

the

DFF.

Figure

3.26:

Timing

Diagram

Of

the

D

Flip

Flop

32

In

this

experiment

CPLD

was

used

as

a

DFF

and

the

NE555

IC

(timer)

supply

the

required

clock

pulse

to

the

CPLD(pre-defined

pin)

and

it

has

connected

LED

act

as

a

clock

state

indicator.

Following

Figure

3.27

shows

the

clock

state

indicato.

Figure

3.27:

Bottom

LED

act

as

a

Clock

State

Indicator

3.6.2

Procedure

1.

DFF

was

designed

by

using

VHDL

Programming.

Following

Figure

3.28

shows

the

VHDL

Code

of

the

DFF.

Figure

3.28:

VHDL

Code

for

DFF

33

2.

Then

design

code

was

synthesized

and

user

constrains

were

added

for

the

design

and

program

was

downloaded

to

the

CPLD.

Following

Figure

3.29

shows

the

pin

assignment

of

the

DFF

design.

Figure

3.29:

Pin

assignment

of

the

DFF

3.6.3

Results

and

Observation

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

BCD

to

SSD

decoder

to

switches

and

SSD.

Following

Figure

3.30

shows

Observed

results

of

the

Digit

Test

of,

the

BCD

to

SSD

decoder.

(a)

switches

input

:1

,

LED

ON

(b)

switches

input

:0

,

LED

OFF

Figure

3.30:

Output

of

a

D

Flip

Flop

device

when

varying

input.

34

3.7

Experiment

7

:

A

State

Machine

Using

VHDL

Programming(

MOD10

Counter

).

3.7.1

Theory

In

this

experiment,

Mod

10

Counter

was

implemented

Using

VHDL

and

to

do

that

concept

of

Finite

State

Machine

(FSM)

used

to

develop

this

counter.

In

general

state

machine

is

a

device

that

store

particular

state

at

a

given

time,these

state

can

be

change(state

transition)

on

inputs

and

it

can

cause

change

on

output

as

well.

But

all

these

states

are

user

configurable

because

FSM

only

changes

its

state

one

at

a

time

only.Figure

3.31

given

below

shows

the

state

diagram

of

a

Mod

10

Counter.

Figure

3.31:

State

Diagram

of

a

mod

10

counter

with

enable

and

reset

In

this

experiment

CPLD

was

used

as

a

DFF

and

the

NE555

IC

(timer)

supply

the

required

clock

pulse

to

the

CPLD(pre-defined

pin)

and

it

has

connected

LED

act

as

a

clock

state

indicator(

refer

figure

3.27.)

35

3.7.2

Procedure

1.

Mod

10

counter

was

designed

by

using

VHDL

Programming.

Following

Figure

3.32

shows

the

VHDL

Code

of

the

Mod

10

counter

with

enable

and

reset.

(a)

part-a-

(b)

part-b-

Figure

3.32:

VHDL

code

of

the

Mod

10

counter

with

enable

and

reset.

2.

Then

design

code

was

synthesized

and

user

constrains

were

added

for

the

design

and

program

was

downloaded

to

the

CPLD.

Following

Figure

3.33

shows

the

pin

assignment

of

the

Mod

10

counter

design.

Figure

3.33:

Pin

assignment

of

the

Mod

10

counter

3.

Then

VHDL

code

of

Mod

10

counter

was

simulated

by

using

ModelSim

to

verify

the

process.

36

3.7.3

Results

and

Observation

1.

After

Simulated

ModelSim

gives

following

wave

patterns

as

a

result.

Figure

3.34

and

Figure

3.35

shows

the

wave

patterns

of

the

mod

10

counter.

Figure

3.34:

a

:

Wave

pattern

of

the

mod

10

counter

Figure

3.35:

b

:

Wave

pattern

of

the

mod

10

counter

Figure

3.35

also

shows

when

enable(below

the

clock

pattern)

is

�high�

the

state

will

be

stored

until

enable

gets

�low�

value

as

described

in

mod

10

counter

state

machine.

37

2.

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

mod

10

counter

to

LEDs.

Following

Figure

3.36

and

Figure

3.37

shows

Observed

results

of

the

mod

10

counter.

(a)

LEDs

output

:

0000

(b)

LEDs

output

:

0001

(c)

LEDs

output

:

0010

(d)

LEDs

output

:

0011

(e)

LEDs

output

:

0100

(f)

LEDs

output

:

0101

Figure

3.36:

a:

Results

of

the

mod

10

counter.

38

(a)

LEDs

output

:

0110

(b)

LEDs

output

:

0111

(c)

LEDs

output

:

1000

(d)

LEDs

output

:

1001

Figure

3.37:

b:

Results

of

the

mod

10

counter.

3.

Figure

3.38

Shows

results

of

the

mod

10

counter

when

reset

button

is

active,

(a)

Figure

3.38:

When

Reset

is

active

39

3.8

Experiment

8

:

Synthesis

of

Components

3.8.1

Theory

In

this

experiment

we

are

using

previous

experiment

files

to

add

as

a

single

file

as

a

components,

In

order

to

accomplished

that

in

here

�BCD

to

SSD

decoder

�(

Refer

Experiment

3.5

for

more

information

)

and

�Mod

10

Counter

�(

Refer

Experiment

3.7

for

more

information

)

added

as

a

components

of

the

main

VHDL

code

to

simply

make

automatic

Counter

to

SSD

decoder.

In

Figure

3.39

shows

the

added

files

as

components

to

the

main

file.

Figure

3.39:

Component

added

to

the

main

file

3.8.2

Procedure

1.

Counter

to

SSD

decoder

was

designed

by

using

VHDL

Programming.

Following

Figure

3.40

shows

the

VHDL

Code

of

the

Counter

to

SSD

decoder

with

enable

and

reset.

(a)

part-a(

b)

part-b-

Figure

3.40:

VHDL

code

of

the

Counter

to

SSD

decoder

with

enable

and

reset.

40

2.

Then

design

code

was

synthesized

and

user

constrains

were

added

for

the

design

and

program

was

downloaded

to

the

CPLD.

Following

Figure

3.41

shows

the

pin

assignment

of

the

Counter

to

SSD

decoder

design.

Figure

3.41:

Pin

assignment

of

the

Counter

to

SSD

decoder

3.8.3

Results

and

Observation

1.

After

implementing

the

design

and

assigning

user

constrains,

Programming

Board

used

to

connect

I/O

of

the

Counter

to

SSD

decoder

to

LEDs.

Following

Figure

3.42

shows

Observed

results

of

the

Counter

to

SSD

decoder.

(a)

(b)

(c)

(d)

Figure

3.42:

Results

of

the

Counter

to

SSD

decoder.

41

2.

Figure

3.43

Shows

results

of

the

Counter

to

SSD

decoder

when

reset

button

is

active,

(a)

Figure

3.43:

When

Reset

is

active

42

Chapter

4

Discussion

and

Conclusion

4.1

Discussion

We

can

choose

schematic

design

method

from

Xilinx

ISE

as

mention

before

in

Section

2.2.

Schematic

design

type

is

the

one

of

the

easiest

design

method

to

program

CPLD

also

it

reduces

some

amount

of

memory

than

other

methods.

But

the

main

disadvantage

is

schematic

method

is

not

a

good

method

when

it

comes

to

very

complex

designs,

because

in

sche



rev

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