Highly Compact Area Efficient Design

Published Date: 02 Nov 2017

E.Sangeetha

PG Scholar

Adhiparasakthi Engineering College

Melmaruvathur, India

e-mail: [email protected]

M.Thilagar

AP/ECE

Adhiparasakthi Engineering College

Melmaruvathur, India

e-mail: [email protected]

Abstract—Reduction of power consumption and area of the circuit is very important for low power VLSI applications. In this work, Ripple Carry Adder using new 9T full-adder cell is designed to operate in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement sum and carry module and also remarkably reduces power and improves temperature sustainability and speed when compared with other full-adder circuits. Therefore, in a nut shell the proposed adder circuit performs better than the existing adders in sub-threshold region and proves to be a feasible option for ultralow-power and energy-efficient applications. The proposed circuit is simulated and the results are evaluated. For simulation, MICROWIND 3.1 tool is used.

Keywords—Full-adders, power consumption, speed, sub-threshold region.

I.INTRODUCTION

Developments in CMOS technology have encouraged the interest in the design of various operational units of different digital systems. The trend of employing integrated circuits in telecommunication and consumer electronics continues, with very important allegations for power efficient VLSI and systems designs. Usually CMOS circuits are used as building blocks for Digital integrated circuits. Power consumption have been made as a major concern in VLSI design by the continuing reduction in feature size of CMOS circuits and corresponding improvement in chip density and operating frequency. Excessive power dissipation in integrated circuits limits their application in portable environment and causes overheating which degrades the chip life and limits the performance [1].

Hence the operation in these devices need to be worked using low-power, area efficient circuits operating at greater speed. The design of high-speed and low-power VLSI architectures requires an efficient arithmetic processing units, which are enhanced for the performance parameters, namely, speed and power consumption [2]. Addition is one of the widely used fundamental arithmetic operations. In addition to its core task, which is summing two binary numbers, it is the heart of many other useful operations such as subtraction, multiplication, and division. An indispensable component for designing various types of processors, specifically, digital signal processors (DSP), microprocessors, and so forth is the full adder circuits. Therefore, limiting the power consumption in full adders, will degrade the overall power consumption of the whole system [3].

There are several issues associated to the full adder namely power consumption, performance, area, noise immunity and good driving ability [4]. Several works have been performed in order to reduce the transistor count and consequently decrease power consumption and area [5]. In some designs, reducing transistor count has developed the threshold loss problem that causes non-full swing outputs , low speed and low noise immunity especially when they are used in cascaded fashion. The critical path that affects the overall speed of the digital system. The adder topology is chosen in such a way that it would provide the desired performance. Hence the performance of the 1-bit full adder cell must be improved and it is the core design aspect [6].

One way to achieve ultralow is by operating digital circuits in sub-threshold mode. When the gate-to-source voltage (VGS) of a transistor is lower than its threshold voltage (VTH), sub-threshold current of an MOSFET transistor exists. If gate-source voltage is larger than threshold voltage, majority carriers are revolted from the gate area of the transistor and a minority carrier channel is created. This is referred to as strong-inversion In this region, more minority carriers are existed in the channel than majority carriers. When VGS is lower than VTH, there are fewer minority carriers in the channel, but their presence comprises a current and the state is referred to as weak-inversion. Sub-threshold parasitic leakage current occurs in the standard CMOS circuit design, but if the supply voltage (VDD) is reduced below the threshold voltage, the circuit can be operated using the sub-threshold current with ultralow-power consumption.

The proposed circuit operates professionally in sub-threshold region to achieve ultralow power. Results exhibits enhancement in power, speed and temperature sustainability over the other adders with comparable performance. In addition the size of the circuit also small compared to other adder circuits. The rest of the paper is organized as follows. Section 2 briefly mentions the previous work reported in the literature. Proposed 9T Adder cell is reported in section 3. The simulation results are presented in section 4 and conclusions are drawn in section 5.

II. PREVIOUS WORK

A full adder does the addition of two bits A and B with the input Carry (Cin) bit generated in the previous stage and produces the output of sum and carries Cout. Full Adder using CMOS Logic and will be called as Conventional CMOS design [8].

A. CONVENTIONAL 28T CMOS FULL ADDER:

The 28T CMOS full adder adder was relayed on regular CMOS structure (pull-up and pull-down network) shown in Fig.1. Cout is generated first using equation 2. Then the sum is derived from the sum using equation 3. The high noise margins and thus reliable operation at low voltages was the one of the most significant benefit of this full adder. Due to the complementary transistor pairs, the layout of CMOS gates was also simplified [2]. The core limitation of this full adder is the use of substantial number of transistors results in high input loads, more power consumption and larger silicon area.

Fig. 1 28T Conventional CMOS Full Adder

B. 20 T TRANSMISSION GATE FULL ADDER:

Transmission gate full adder produces buffered outputs of proper polarity for both carry and sum output with the limitations of high power consumption [9].

Fig 2. 20T Transmission Gate Full Adder

In the Fig. 2, two transmission gates are followed by the two inverters which act as 8-T XOR. To generate sum, Cin and Cout are multiplexed which can controlled by either (A Xor B) or (A Xnor B). Similarly the output carry can be generated by multiplexing A and Cin which is controlled by (A Xor B). The main advantage is the fastest adder so far been reported. The circuit is simpler than the conventional adder [10]. The limitation is the power dissipation in this circuit is higher than the 28T adder. However with same power consumption it performs faster.

C. 10T STATIC ENERGY RECOVERY FULL ADDER:

In 10T static energy recovery full adder of adder, the charge is reused by the energy recovering logic and therefore consumes less power than non-energy recovering logic. This circuit is composed of two XNORs realized by 4 transistors. Sum is produced from the output of the second stage XNOR circuit [3]. By multiplexing A and Cin controlled by (A ⊗ B) The cout can be estimated. Initially when A=B=0 and then a changes to 1. The capacitor is charged by VDD when both the inputs are equal to zero . The capacitor discharges through A when B reaches a high voltage level maintaining a fixed at a low voltage level. Some charge is retained in A. Hence it is not required to charge it fully when A reaches a high voltage level. Hence the energy consumption is reduced [11]. There is no direct route to the ground in the new SERF adder. The power consumption is minimized by the elimination of a path to the ground. The charge stored at the load capacitance is then again applied to the control gates the energy-recovering full adder is made as an energy efficient design by the organization of absence of a direct path to ground and the re-application of the load charge to the control gate [12]. The full-swing at the output nodes is produced by the circuit. But it fails to provide so for the internal nodes. The circuit becomes slower due to the power consumption by the circuit. It cannot be cascaded at low power supply due to multiple threshold problems is its core limitation [13].

III. PROPOSED 9T FULL ADDER DESIGN

The full adder performs the addition of the three 1-bit inputs are A, B, and Cin [14]. The circuit shown in Fig. 3 is the schematic of modified 8T full adder cell using an extra transistor M9 to improve the operation of the 8T full adder cell [15]. A EXOR of the three inputs in addition to an extra transistor M9 cell is used to obtain the sum output. Output carry is implemented using 2T multiplexer. 8T full adder is encountered with problems for certain input vectors [16]. This problem is eliminated in the design of Fig. 7 by adding an extra transistor M9. Its power consumption is reduced than the 8T adder circuit besides having an area overhead of one transistor [17]. The outputs have good logic level only for certain input vectors. There is a major mortification of output voltage for the remaining input vectors, that may lead to functional failure and also enhanced power consumption at higher voltages. A transistor M9 stay switched ON for input pattern 010 and 100 but does not sponsor to produce sum output and hence results into excess power consumption. C:\Users\APEC\AppData\Local\Microsoft\Windows\Temporary Internet Files\Content.Word\New Picture (39).bmp

Fig. 3 Existing 1-bit 9T full adder design I.

Fig. 4 shows schematic of another 9T full adder design II. In this circuit, sum is implemented using a three-transistor XOR gate and a multiplexer and the output carry is implemented using one multiplexer. The output of first stage XOR is evaluated from the output multiplexer’s selector stage. This circuit shows enhancement in power when compared with adder of Fig. 3 in sub-threshold region. The table II shows the justification for less power consumption than the circuit of Fig. 3. The schematic of proposed 9T full adder cell is shown in Fig. 5 and its truth table is stated in Table I. The operating principle of proposed circuit is different from ordinary circuits. In order to estimate the sum output of the proposed design, the truth table has been partitioned into two segments, one for input A = "0" and another for A = "1" rather than implementing the conventional sum module.

Fig. 4 Existing 1-bit 9T full adder design II.

It is proven that when A = "0", Sum can be produced by XORing inputs B and Cin. correspondingly, when A = "1", Sum is estimated by the XNOR operation between inputs B and input carry. Therefore, the operation of Sum module is relayed on implementing XOR operation and XNOR operation between inputs B and input carry. The logic for carry output is computed from equation (1) and (2).

When B xor Cin = 0,

Cout = Cin (1)

When B xor Cin = 1,

Cout = A (2)

In order to generate XNOR function, an inverter is coupled at the output of first-stage XOR gate. Finally by transferring these output levels through 2T multiplexer, sum is implemented. The XOR of B and Cin is the input of the PMOS (M6) of 2T multiplexer while XNOR of B and Cin is the input of NMOS (M7). The input A regulates the 2T multiplexer. The output carry is implemented by using another 2T multiplexer which is regulated by output of first-stage XOR gate and channels either A or input carry correspondingly. This circuit degrades the overall power delay product at varying input voltages and operating frequencies and also enhances the temperature sustainability while operating in sub-threshold region. The most demanding design constraint for developing compact systems, that is, area, maintains stable for all three designs.

Table I. Truth table of 1-bit full adder.

A

B

Cin

Sum

Cout

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Entire power consumption in MOS logic devices is expressed as sum of three components as the average switching power consumption, sub-threshold power consumption and power dissipation due to short circuit leakage current. In this circuit, the current is diminished by the reduced value of VGS in sub-threshold mode exponentially and thus degrades the sub-threshold power.

Fig. 5 Proposed 9T full adder cell.

Short circuit power dissipation is due to the high value of rise and fall times of input voltage. Node N2, where the main logic has been implemented, exhibits the diversity between the prosed and existing full adder circuit. The power consuming transitions at node N2 are lower than the existing ones in the proposed 9T full adder circuit due to the lower number of power consuming transitions. The operative number of power consuming transitions at each internal node is shown in table II. In a nutshell, the proposed 9T full adder circuit is an excellent option for low-power compact systems. In order to eliminate the substrate-bias effect, all the substrate terminals of the 9T full adders are coupled to their respective source terminals. Due to only a few number of transistors employed in the circuit, this design of proposed full adder seems to be area efficient. The performance of circuit relaying on the speed and delay of the full adder is discussed in the future work.

Table II. No. of power consuming transitions at different internal nodes

9T Full adder Design-I

9T Full adder Design-II

Proposed 9T full adder

N1 N2 N3

1 4 3

N1 N2 N3

1 3 3

N1 N2 N3

2 2 3

Total = 8

Total = 7

Total = 7

IV. SIMULATION RESULTS

Low-power full-adder cells are designed using 9 transistors that lead to less number of transistor count and low power consumption. The commonly used software to obtain the simulation output of the full adder cell is MICROWIND 3.1. The DSCH program is one of the modules of MICROWIND tool, which is used for simulation. The voltage versus time waveforms of the proposed 9T Full Adder cell is shown in Fig. 6. From the figure it is evident that the power consumption of the proposed new adder cell is obtained as 4.556μW. The figure also exhibits delay achieved to produce the output.

Fig. 6 Voltage vs. Time Waveform of proposed 1-bit 9T Full Adder.

The 4-bit full (Ripple Carry) adder circuit constructed by using the 4 proposed 9T full adder circuits connected in a cascaded fashion and is simulated using MICROWIND simulation tool. The voltage versus time waveform of the 4-bit full (Ripple Carry) adder circuit is shown in Fig. 7, which also estimates the total power consumption of the circuit. Power consumption of the various 1-bit full adder circuits for power supply voltage of 1.2V are given in the Table III. The total power consumption of the circuit can also be analyzed under different voltages.

Table III. Power consumption of various 1-bit full adder circuits

FULL ADDER SCHEME

TRANSISTOR COUNT

POWER

(W)

Split-path D3L

30

0.770m

CPL

32

0.761m

14T

14

0.231m

20T(Transmission–Gate Adder )

20

0.224m

Hybrid

28

15.307µ

CMOS

28

11.411 µ

10T

10

5.783 µ

Proposed 9T

9

4.556 µ

The 8-bit full (Ripple Carry) Adder can be constructed using the proposed 9T 1-bit full adder for the ultra low-power application. It consumes a small amount of power and less number of transistors compared to other full adder technique. It will be compact and area efficient.

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Fig. 7 Voltage vs. time waveform of the 4-bit full (Ripple Carry) adder circuit

The power consumption comparison of 8-bit full (Ripple Carry) adder constructed using different 1-bit full adder topology for the power supply voltage of 1.2V is shown in the table IV.

Table IV Power consumption of various 8-bit full (Ripple Carry) adders

FULL ADDER SCHEME

TOTAL TRANSISTOR COUNT

POWER

(W)

Split-path D3L

240

6.010m

Hybrid

224

13.656 µ

CMOS

224

15.115µ

Proposed 9T

72

2.088 µ

V. CONCLUSION

The proposed work results in the reduction of power consumption of 8-bit full (Ripple Carry) adder circuit which is constructed using the proposed 9T 1-bit full adder scheme. Hence this type of full adder circuits can be used in the ultra low-power application. The proposed 9T full adder circuit is highly compact due to usage of only a few number of transistors compared to other full adder topology. Thus the 8-bit full (Ripple Carry) adder constructed using proposed 9T full adder topology is highly area efficient design compared to other full adder configuration. Due to presence of lower delay, the speed of the proposed full adder circuit is increased.

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