Dielectric Is An Insulator

Published Date: 02 Nov 2017

Introduction

Dielectric is a material that has a high resistant in current flow and the other terms for dielectric is an insulator. Dielectrics have no loosely bound electrons in the valence shell but for electric conduction have a high energy gap to keep valence band electron to move out of the conduction band. The flow current between opposite charge pole is keeping the minimum and the electrostatics lines fluxes are not impeded. So, an electrostatic can store energy and it’s so useful in capacitor especially for radio frequencies, so electrostatic are used in the radio frequency transmission line.

The materials of dielectric usually are from solid materials likeporcelain (ceramic), mica, glass, plastics, rubber and somes dielectric materials are silicon dioxide (SiO2), silicon nitride (Si3N4) and polymide for plastic material. The example for good material of an dielectric with a resistivity of about 18 x 106 ohm-cm are deionized water (DI). In DI water have insufficient free electron to sustain current flow from a small battery. Dry air is the best dielectric and its ised in a capacitors technology and types of transmission lines.

More lower the dielectric loss, the more effective is a dielectric material. However, the conductivity of dielectric still can be improved by adding an impurity to water such as the table salt. From that adding that impurity material the salt dissociates in water into its basic ionic elements of sodium (Na+) and chlorine (Cl-) forming an electrolyte. The net effect of these charged atoms is the same as having free electrons in a piece of copper wire and if there are sufficient charged atoms, current flow can sustain. Materials with moderate dielectric constant include ceramic, distilled water, paper, mica, polythe\ylene and glass have a high dielectric constants. The adding of impurity materials to alter dielectric material’s conductivity is an important aspect for semiconductor technology.

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Capacitance is the storage of the electrical charge and dielectric is used in a capacitor built-in to separated two on conductive plates. The units for capacitance is farads and the amount of charged can store in capacitor is depends to their on certain physical characteristics include the area of the plates, better known as dielectric constant, k (farads/cm). x. We can use a simple circuit like below

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We can explained how a capacitor holds an electrical charge like figure below. In a figure below, a battery is connected to a capacitor and when the switch is closed the electrons from the left metal plate are attracted to the positive part of the battery. For the electrons from the negative part of the battery will flow to the right plate to balance the deficiency of electrons from the left part. The initial currents stops due to the electric material between the plates. There is a difference between the two plates and an electrostatic field exists between the charge plates.

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Furthermore,if the battery and the circuit are removed from the capacitor, the left plate will are positively charge and the other part of plate will be a negative charge. As a result, the overall differences in potential is equal to the original battery value and remains as long as there is no other way for electrons to flow to the opposites side of the capacitor . From this example we can know the concept regarding how a capacitor works is crucial for understanding how a field-effect transistor works.

Dielectric Performance

There are two important aspects of dielectric are the dielectric constant (k) and device isolation. The dielectric materials used in different film layers directly affect the performance of a microchip or semiconductor device.

The dielectric constant (k) is a non-conductive material represents the effectiveness at storing charge under the influence of a electric field. Its mean this is to the insulating material’s ability to act like a capacitor. The lowestattainable of k is air (1.0) and the highest k dielectric stores more electric or charge energy. The other value of k are likes silicon dioxide (SiO2, 3.9), plasma enchance CVD (PECVD,4.1 to 4.3. (4)

For low-k constant dielectric requirements that have some researched the impact of using several promising low dielectric constant materials as inter-level dielectrics for high performance VLSI/ULSI interconnect applications. The materials under study spin-on deposited materials which include such as fluorinated polyamide, silsesquioxane, fluorinated poly (arylethers) and perfluorocyclobutane with dielectric constants ranging from 2.3 to 2.8. Compared to other spin-on deposited materials they have relatively high thermal stability and better process compatibility. Furthermore, inter-line capacitance, dielectric leakage current, metal layer resistivity, and interconnect metal linewidth was monitored as the wafers went through different thermal stress conditions. Moreover, the electrical and reliability properties were compared between interconnect structures using new low dielectric constant materials and structures using conventional SiO, sub 2 deposited by plasma enhanced chemical vapor deposition and the results are useful for determining how to use these new low dielectric constant materialin high performance ULSI interconnecting processing.(5) At the figure below shows the typical requirements for a low dielectric constant film for introduction into wafer fabrication.

In a high k dielectric constant the spin-coating process was adopted in the fabrication of capacitors on the materials with a trip-roller the materials were mixed with resins to increase dielectric constant of capacitors. We have added high dielectric ceramic powder and aluminum powder to ITK5517 resin, the conductive powder using the interface polarization mechanism to promote polymer Ceramic composite materials dielectric constant was investigated. As a result of this process show that polymer-ceramic composite materials, the dielectric characteristics are slightly increased with the increasing amount of ceramic powder. Furthermore, the dielectric constant significantly increases with increasing the amount of the added aluminum but dielectric losses remain within a constant range for conductive polymer ceramic Powder composite materials.(6)

There is another one ongoing investigation in the industry for a high-k dielectric materials primarily DRAM storage capacitors and as an eventual replacement for the extremely thin gate oxide (in 20 A for 0.18um devices). This technology has undergone a 4 times increase in storage density every three years for the past 25 years due to processing and design for an improvements. To achieved the required charge storage with SiO2 DRAM storage cell design has evolved into complex stacked capacitor structures. If we are using the high-k dielectric constant a simpler stack structure will be used for lower fabrication costs and also can be easily to integrated into the existing process. There is some weakness when using high-k dielectric constants because DRAM memory cells are sensitive due to leakage and breakdown voltage of storage material and interfaces. To compared the DRAM memory cells that required a thicker Ta2O5 reduces its benefit. Furthermore, there is another potential for high k material is barium strontium titanate (BST) which gives a significant improvement in capacitance per unit area over conventional dielectrics. This area of gate dimensions in ULSI circuitry the electrons can tunnel through the gate material when the transistor is switched on and off and also this leads to threshold voltage drift and eventual circuit failure because the device cannot switch states.

The best performance for a capacitor application are in great demands, for which high dielectric constant (k) , low dielectric loss and process compatability with the printed circuit board’s (PCB) are the most important requirements.(3) We can increase the performance of the dielectric of the high k nano-composites by the selection of the appropriate filler, its size, size distribution, surface property and morphology. There is have significant influence on the dielectric properties of the nanocomposites system for the size and size distribution of metal nanoparticles in the nanocomposites. More smaller size and narrow size distribution of Ag nanoparticles resulted in lower dielectric loss tangent and also the nanoparticles on the dielectric properties of the nanocomposites revealed that assembly of the nanoparticles impact the dielectric performance of the nanocomposites in terms of the polarization and conducting property Furthermore, the Ag nanocomposites containing Ag nanoparticle with more discrete morphology rendered much lower dielectric loss tanger compared to the nanocomposites with Ag nanoparticles of more aggregated morphology.(3-4)

For example doped SiO2 are the most common interlayer dielectric (ILD) material. In a researcher and development is underway to replace doped SiO2 for the ILD with another types of dielectric material has a low dielectric constant. Its important because reducing the k value can reduces the capacitive loose between adjacent conductor because the dielectric stores less electric field and therefore take less time to charge, allowing for an increase in speed performance of the metal conductors. For a low-k dielectric material its becomes critical smaller linewidths with less spacing between metal lines and when the metal linewidth decrease the capacitive effects of an conductors and insulator increase and with using low k also compensates for this.

The other factors that can effect the performances of dielectric is a device isolation. Device isolation can referred in MOS wafer fabrication between the devices in wafer. With this technique it can reduces parasitic field transistor in MOS planar fabrication. The process isolation must accommodate scaling between the different devices technology gate oxide thickness and junction depth. The space allocated with devices isolation will reduces for high performances IC’s. There is two basics techniques in devices isolation on MOS technology is local oxidiation and shallow trench isolation. The difference for this two techniques is their final oxide shapes and process flow.

Local oxidiation of silicon (LOCOS) is the traditional technique when the layer is grown on the wafer with the critical dimensions of 0.35 um and large. After layer of silicon nitride is deposited that used as an oxide barrier and the pattern transfer is photolithography. After that the pattern is etched into the nitride. The next step is the growth of the thermal oxide and this is the main step for this techniques and last step is the removal of the nitride layer. LOCOS isolation structure are too big for isolation in devices with deep submicron scaling. (59) The main drawback of this technique is ‘birds beak effect’ and the surface area which is lost to this encroachment. This techniques uses patterned island of silicon nitride to define the region for oxidation growth. The advantages of this techniques are the high oxide quality and the siple process flow because the structure is thermally grown. LOCOS also is not acceptable for high density ULSI technology.Figure below is the process sequence for LOCOS.

\includegraphics[width=0.6\linewidth]{fig/LOCOS4}

Figure 1.1: Process sequence for local oxidation of silicon (LOCOS).

The others technique in devices isolation in MOS planar fabrication is the shallow trench isolation (STI). STI is preferred isolation process for wafers at the 0.25 um and below technology nodes. There is some reason why STI must be used compared than LOSCOS :

The need for more robust devices isolation, especially DRAM devices

A significant reduction in the surface area for transistor isolation

Superior latchup protection

No channel encroachment

Compability with chemical mechanical planarization (CMP)

Compared than LOCOS, STI is completely avoids the birds beak shape characteristics because this isolation technique for the sub 0.5 um technology. STI are more suitable to improve density requirements with the zero oxide foeld encroachment. There is start with the same process of LOCOS by etched into silicon substrate. After that also a thermal oxide but in STI has stopped after the formation of a thin oxide layer. The rest is filled with a deposited oxide. Nest process is deposited oxide is removed with chemical planarization and lastly the nitride mask is also removed. There is the differences STI than LOCOS :

STI is etched into silicon substrate

The price for saving space space with STI

\includegraphics[width=0.9\linewidth]{fig/STI1}

Figure 1.2: Steps in shallow trech isolation process flow.